72ed5a8c9b
This patch is adding a ASoC driver for the cs42l51 from Cirrus Logic. Master mode and spi mode are not supported. Signed-off-by: Arnaud Patard <apatard@mandriva.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.ul> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
163 lines
5.4 KiB
C
163 lines
5.4 KiB
C
/*
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* cs42l51.h
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*
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* ASoC Driver for Cirrus Logic CS42L51 codecs
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*
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* Copyright (c) 2010 Arnaud Patard <apatard@mandriva.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CS42L51_H
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#define _CS42L51_H
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#define CS42L51_CHIP_ID 0x1B
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#define CS42L51_CHIP_REV_A 0x00
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#define CS42L51_CHIP_REV_B 0x01
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#define CS42L51_CHIP_REV_ID 0x01
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#define CS42L51_MK_CHIP_REV(a, b) ((a)<<3|(b))
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#define CS42L51_POWER_CTL1 0x02
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#define CS42L51_POWER_CTL1_PDN_DACB (1<<6)
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#define CS42L51_POWER_CTL1_PDN_DACA (1<<5)
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#define CS42L51_POWER_CTL1_PDN_PGAB (1<<4)
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#define CS42L51_POWER_CTL1_PDN_PGAA (1<<3)
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#define CS42L51_POWER_CTL1_PDN_ADCB (1<<2)
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#define CS42L51_POWER_CTL1_PDN_ADCA (1<<1)
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#define CS42L51_POWER_CTL1_PDN (1<<0)
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#define CS42L51_MIC_POWER_CTL 0x03
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#define CS42L51_MIC_POWER_CTL_AUTO (1<<7)
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#define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5)
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#define CS42L51_QSM_MODE 3
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#define CS42L51_HSM_MODE 2
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#define CS42L51_SSM_MODE 1
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#define CS42L51_DSM_MODE 0
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#define CS42L51_MIC_POWER_CTL_3ST_SP (1<<4)
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#define CS42L51_MIC_POWER_CTL_PDN_MICB (1<<3)
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#define CS42L51_MIC_POWER_CTL_PDN_MICA (1<<2)
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#define CS42L51_MIC_POWER_CTL_PDN_BIAS (1<<1)
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#define CS42L51_MIC_POWER_CTL_MCLK_DIV2 (1<<0)
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#define CS42L51_INTF_CTL 0x04
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#define CS42L51_INTF_CTL_LOOPBACK (1<<7)
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#define CS42L51_INTF_CTL_MASTER (1<<6)
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#define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3)
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#define CS42L51_DAC_DIF_LJ24 0x00
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#define CS42L51_DAC_DIF_I2S 0x01
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#define CS42L51_DAC_DIF_RJ24 0x02
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#define CS42L51_DAC_DIF_RJ20 0x03
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#define CS42L51_DAC_DIF_RJ18 0x04
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#define CS42L51_DAC_DIF_RJ16 0x05
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#define CS42L51_INTF_CTL_ADC_I2S (1<<2)
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#define CS42L51_INTF_CTL_DIGMIX (1<<1)
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#define CS42L51_INTF_CTL_MICMIX (1<<0)
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#define CS42L51_MIC_CTL 0x05
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#define CS42L51_MIC_CTL_ADC_SNGVOL (1<<7)
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#define CS42L51_MIC_CTL_ADCD_DBOOST (1<<6)
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#define CS42L51_MIC_CTL_ADCA_DBOOST (1<<5)
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#define CS42L51_MIC_CTL_MICBIAS_SEL (1<<4)
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#define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2)
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#define CS42L51_MIC_CTL_MICB_BOOST (1<<1)
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#define CS42L51_MIC_CTL_MICA_BOOST (1<<0)
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#define CS42L51_ADC_CTL 0x06
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#define CS42L51_ADC_CTL_ADCB_HPFEN (1<<7)
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#define CS42L51_ADC_CTL_ADCB_HPFRZ (1<<6)
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#define CS42L51_ADC_CTL_ADCA_HPFEN (1<<5)
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#define CS42L51_ADC_CTL_ADCA_HPFRZ (1<<4)
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#define CS42L51_ADC_CTL_SOFTB (1<<3)
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#define CS42L51_ADC_CTL_ZCROSSB (1<<2)
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#define CS42L51_ADC_CTL_SOFTA (1<<1)
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#define CS42L51_ADC_CTL_ZCROSSA (1<<0)
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#define CS42L51_ADC_INPUT 0x07
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#define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6)
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#define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4)
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#define CS42L51_ADC_INPUT_INV_ADCB (1<<3)
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#define CS42L51_ADC_INPUT_INV_ADCA (1<<2)
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#define CS42L51_ADC_INPUT_ADCB_MUTE (1<<1)
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#define CS42L51_ADC_INPUT_ADCA_MUTE (1<<0)
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#define CS42L51_DAC_OUT_CTL 0x08
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#define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5)
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#define CS42L51_DAC_OUT_CTL_DAC_SNGVOL (1<<4)
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#define CS42L51_DAC_OUT_CTL_INV_PCMB (1<<3)
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#define CS42L51_DAC_OUT_CTL_INV_PCMA (1<<2)
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#define CS42L51_DAC_OUT_CTL_DACB_MUTE (1<<1)
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#define CS42L51_DAC_OUT_CTL_DACA_MUTE (1<<0)
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#define CS42L51_DAC_CTL 0x09
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#define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6)
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#define CS42L51_DAC_CTL_FREEZE (1<<5)
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#define CS42L51_DAC_CTL_DEEMPH (1<<3)
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#define CS42L51_DAC_CTL_AMUTE (1<<2)
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#define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0)
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#define CS42L51_ALC_PGA_CTL 0x0A
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#define CS42L51_ALC_PGB_CTL 0x0B
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#define CS42L51_ALC_PGX_ALCX_SRDIS (1<<7)
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#define CS42L51_ALC_PGX_ALCX_ZCDIS (1<<6)
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#define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0)
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#define CS42L51_ADCA_ATT 0x0C
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#define CS42L51_ADCB_ATT 0x0D
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#define CS42L51_ADCA_VOL 0x0E
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#define CS42L51_ADCB_VOL 0x0F
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#define CS42L51_PCMA_VOL 0x10
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#define CS42L51_PCMB_VOL 0x11
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#define CS42L51_MIX_MUTE_ADCMIX (1<<7)
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#define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0)
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#define CS42L51_BEEP_FREQ 0x12
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#define CS42L51_BEEP_VOL 0x13
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#define CS42L51_BEEP_CONF 0x14
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#define CS42L51_TONE_CTL 0x15
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#define CS42L51_TONE_CTL_TREB(x) (((x)&0xf)<<4)
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#define CS42L51_TONE_CTL_BASS(x) (((x)&0xf)<<0)
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#define CS42L51_AOUTA_VOL 0x16
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#define CS42L51_AOUTB_VOL 0x17
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#define CS42L51_PCM_MIXER 0x18
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#define CS42L51_LIMIT_THRES_DIS 0x19
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#define CS42L51_LIMIT_REL 0x1A
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#define CS42L51_LIMIT_ATT 0x1B
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#define CS42L51_ALC_EN 0x1C
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#define CS42L51_ALC_REL 0x1D
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#define CS42L51_ALC_THRES 0x1E
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#define CS42L51_NOISE_CONF 0x1F
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#define CS42L51_STATUS 0x20
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#define CS42L51_STATUS_SP_CLKERR (1<<6)
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#define CS42L51_STATUS_SPEA_OVFL (1<<5)
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#define CS42L51_STATUS_SPEB_OVFL (1<<4)
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#define CS42L51_STATUS_PCMA_OVFL (1<<3)
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#define CS42L51_STATUS_PCMB_OVFL (1<<2)
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#define CS42L51_STATUS_ADCA_OVFL (1<<1)
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#define CS42L51_STATUS_ADCB_OVFL (1<<0)
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#define CS42L51_CHARGE_FREQ 0x21
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#define CS42L51_FIRSTREG 0x01
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/*
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* Hack: with register 0x21, it makes 33 registers. Looks like someone in the
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* i2c layer doesn't like i2c smbus block read of 33 regs. Workaround by using
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* 32 regs
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*/
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#define CS42L51_LASTREG 0x20
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#define CS42L51_NUMREGS (CS42L51_LASTREG - CS42L51_FIRSTREG + 1)
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extern struct snd_soc_dai cs42l51_dai;
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extern struct snd_soc_codec_device soc_codec_device_cs42l51;
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#endif
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