078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
197 lines
5.3 KiB
C
197 lines
5.3 KiB
C
/*
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* Copyright (C) 2001,2002,2004 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/fw/cfe/cfe_api.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/bcm1480_int.h>
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extern void smp_call_function_interrupt(void);
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/*
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* These are routines for dealing with the bcm1480 smp capabilities
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* independent of board/firmware
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*/
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static void *mailbox_0_set_regs[] = {
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IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU),
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};
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static void *mailbox_0_clear_regs[] = {
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IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU),
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};
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static void *mailbox_0_regs[] = {
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IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CPU),
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};
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/*
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* SMP init and finish on secondary CPUs
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*/
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void bcm1480_smp_init(void)
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{
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unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
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STATUSF_IP1 | STATUSF_IP0;
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/* Set interrupt mask, but don't enable */
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change_c0_status(ST0_IM, imask);
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}
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/*
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* These are routines for dealing with the sb1250 smp capabilities
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* independent of board/firmware
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*/
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/*
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* Simple enough; everything is set up, so just poke the appropriate mailbox
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* register, and we should be set
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*/
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static void bcm1480_send_ipi_single(int cpu, unsigned int action)
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{
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__raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]);
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}
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static void bcm1480_send_ipi_mask(const struct cpumask *mask,
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unsigned int action)
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{
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unsigned int i;
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for_each_cpu(i, mask)
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bcm1480_send_ipi_single(i, action);
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}
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/*
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* Code to run on secondary just after probing the CPU
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*/
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static void bcm1480_init_secondary(void)
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{
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extern void bcm1480_smp_init(void);
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bcm1480_smp_init();
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}
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/*
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* Do any tidying up before marking online and running the idle
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* loop
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*/
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static void bcm1480_smp_finish(void)
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{
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extern void sb1480_clockevent_init(void);
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sb1480_clockevent_init();
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local_irq_enable();
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}
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/*
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* Final cleanup after all secondaries booted
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*/
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static void bcm1480_cpus_done(void)
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{
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}
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/*
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* Setup the PC, SP, and GP of a secondary processor and start it
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* running!
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*/
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static void bcm1480_boot_secondary(int cpu, struct task_struct *idle)
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{
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int retval;
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retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
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__KSTK_TOS(idle),
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(unsigned long)task_thread_info(idle), 0);
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if (retval != 0)
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printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
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}
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/*
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* Use CFE to find out how many CPUs are available, setting up
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* cpu_possible_mask and the logical/physical mappings.
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* XXXKW will the boot CPU ever not be physical 0?
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*
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* Common setup before any secondaries are started
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*/
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static void __init bcm1480_smp_setup(void)
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{
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int i, num;
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init_cpu_possible(cpumask_of(0));
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__cpu_number_map[0] = 0;
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__cpu_logical_map[0] = 0;
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for (i = 1, num = 0; i < NR_CPUS; i++) {
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if (cfe_cpu_stop(i) == 0) {
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set_cpu_possible(i, true);
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__cpu_number_map[i] = ++num;
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__cpu_logical_map[num] = i;
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}
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}
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printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
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}
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static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
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{
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}
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struct plat_smp_ops bcm1480_smp_ops = {
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.send_ipi_single = bcm1480_send_ipi_single,
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.send_ipi_mask = bcm1480_send_ipi_mask,
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.init_secondary = bcm1480_init_secondary,
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.smp_finish = bcm1480_smp_finish,
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.cpus_done = bcm1480_cpus_done,
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.boot_secondary = bcm1480_boot_secondary,
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.smp_setup = bcm1480_smp_setup,
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.prepare_cpus = bcm1480_prepare_cpus,
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};
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void bcm1480_mailbox_interrupt(void)
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{
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int cpu = smp_processor_id();
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int irq = K_BCM1480_INT_MBOX_0_0;
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unsigned int action;
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kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
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/* Load the mailbox register to figure out what we're supposed to do */
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action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff;
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/* Clear the mailbox to clear the interrupt */
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__raw_writeq(((u64)action)<<48, mailbox_0_clear_regs[cpu]);
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if (action & SMP_RESCHEDULE_YOURSELF)
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scheduler_ipi();
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if (action & SMP_CALL_FUNCTION)
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smp_call_function_interrupt();
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}
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