a93de288aa
Change SDRAM timings and other settings as necessary on voltage and frequency changes. We calculate these register settings based on data from the device data sheet and inputs such a frequency, voltage state(stable or ramping), temperature level etc. TODO: frequency and voltage change handling needs to be integrated with clock framework and regulator framework respectively. This is not done today due to missing pieces in the kernel. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
589 lines
19 KiB
C
589 lines
19 KiB
C
/*
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* Defines for the EMIF driver
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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*
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EMIF_H
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#define __EMIF_H
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/*
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* Maximum number of different frequencies supported by EMIF driver
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* Determines the number of entries in the pointer array for register
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* cache
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*/
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#define EMIF_MAX_NUM_FREQUENCIES 6
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/* State of the core voltage */
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#define DDR_VOLTAGE_STABLE 0
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#define DDR_VOLTAGE_RAMPING 1
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/* Defines for timing De-rating */
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#define EMIF_NORMAL_TIMINGS 0
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#define EMIF_DERATED_TIMINGS 1
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/* Length of the forced read idle period in terms of cycles */
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#define EMIF_READ_IDLE_LEN_VAL 5
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/*
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* forced read idle interval to be used when voltage
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* is changed as part of DVFS/DPS - 1ms
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*/
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#define READ_IDLE_INTERVAL_DVFS (1*1000000)
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/*
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* Forced read idle interval to be used when voltage is stable
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* 50us - or maximum value will do
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*/
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#define READ_IDLE_INTERVAL_NORMAL (50*1000000)
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/* DLL calibration interval when voltage is NOT stable - 1us */
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#define DLL_CALIB_INTERVAL_DVFS (1*1000000)
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#define DLL_CALIB_ACK_WAIT_VAL 5
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/* Interval between ZQCS commands - hw team recommended value */
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#define EMIF_ZQCS_INTERVAL_US (50*1000)
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/* Enable ZQ Calibration on exiting Self-refresh */
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#define ZQ_SFEXITEN_ENABLE 1
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/*
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* ZQ Calibration simultaneously on both chip-selects:
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* Needs one calibration resistor per CS
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*/
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#define ZQ_DUALCALEN_DISABLE 0
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#define ZQ_DUALCALEN_ENABLE 1
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#define T_ZQCS_DEFAULT_NS 90
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#define T_ZQCL_DEFAULT_NS 360
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#define T_ZQINIT_DEFAULT_NS 1000
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/* DPD_EN */
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#define DPD_DISABLE 0
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#define DPD_ENABLE 1
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/*
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* Default values for the low-power entry to be used if not provided by user.
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* OMAP4/5 has a hw bug(i735) due to which this value can not be less than 512
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* Timeout values are in DDR clock 'cycles' and frequency threshold in Hz
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*/
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#define EMIF_LP_MODE_TIMEOUT_PERFORMANCE 2048
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#define EMIF_LP_MODE_TIMEOUT_POWER 512
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#define EMIF_LP_MODE_FREQ_THRESHOLD 400000000
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/* DDR_PHY_CTRL_1 values for EMIF4D - ATTILA PHY combination */
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#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY 0x049FF000
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#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY 0x41
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#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY 0x80
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#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY 0xFF
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/* DDR_PHY_CTRL_1 values for EMIF4D5 INTELLIPHY combination */
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#define EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY 0x0E084200
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#define EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS 10000
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/* TEMP_ALERT_CONFIG - corresponding to temp gradient 5 C/s */
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#define TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS 360
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#define EMIF_T_CSTA 3
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#define EMIF_T_PDLL_UL 128
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/* External PHY control registers magic values */
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#define EMIF_EXT_PHY_CTRL_1_VAL 0x04020080
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#define EMIF_EXT_PHY_CTRL_5_VAL 0x04010040
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#define EMIF_EXT_PHY_CTRL_6_VAL 0x01004010
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#define EMIF_EXT_PHY_CTRL_7_VAL 0x00001004
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#define EMIF_EXT_PHY_CTRL_8_VAL 0x04010040
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#define EMIF_EXT_PHY_CTRL_9_VAL 0x01004010
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#define EMIF_EXT_PHY_CTRL_10_VAL 0x00001004
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#define EMIF_EXT_PHY_CTRL_11_VAL 0x00000000
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#define EMIF_EXT_PHY_CTRL_12_VAL 0x00000000
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#define EMIF_EXT_PHY_CTRL_13_VAL 0x00000000
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#define EMIF_EXT_PHY_CTRL_14_VAL 0x80080080
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#define EMIF_EXT_PHY_CTRL_15_VAL 0x00800800
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#define EMIF_EXT_PHY_CTRL_16_VAL 0x08102040
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#define EMIF_EXT_PHY_CTRL_17_VAL 0x00000001
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#define EMIF_EXT_PHY_CTRL_18_VAL 0x540A8150
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#define EMIF_EXT_PHY_CTRL_19_VAL 0xA81502A0
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#define EMIF_EXT_PHY_CTRL_20_VAL 0x002A0540
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#define EMIF_EXT_PHY_CTRL_21_VAL 0x00000000
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#define EMIF_EXT_PHY_CTRL_22_VAL 0x00000000
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#define EMIF_EXT_PHY_CTRL_23_VAL 0x00000000
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#define EMIF_EXT_PHY_CTRL_24_VAL 0x00000077
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#define EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS 1200
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/* Registers offset */
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#define EMIF_MODULE_ID_AND_REVISION 0x0000
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#define EMIF_STATUS 0x0004
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#define EMIF_SDRAM_CONFIG 0x0008
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#define EMIF_SDRAM_CONFIG_2 0x000c
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#define EMIF_SDRAM_REFRESH_CONTROL 0x0010
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#define EMIF_SDRAM_REFRESH_CTRL_SHDW 0x0014
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#define EMIF_SDRAM_TIMING_1 0x0018
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#define EMIF_SDRAM_TIMING_1_SHDW 0x001c
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#define EMIF_SDRAM_TIMING_2 0x0020
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#define EMIF_SDRAM_TIMING_2_SHDW 0x0024
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#define EMIF_SDRAM_TIMING_3 0x0028
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#define EMIF_SDRAM_TIMING_3_SHDW 0x002c
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#define EMIF_LPDDR2_NVM_TIMING 0x0030
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#define EMIF_LPDDR2_NVM_TIMING_SHDW 0x0034
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#define EMIF_POWER_MANAGEMENT_CONTROL 0x0038
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#define EMIF_POWER_MANAGEMENT_CTRL_SHDW 0x003c
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#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
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#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
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#define EMIF_OCP_CONFIG 0x0054
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#define EMIF_OCP_CONFIG_VALUE_1 0x0058
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#define EMIF_OCP_CONFIG_VALUE_2 0x005c
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#define EMIF_IODFT_TEST_LOGIC_GLOBAL_CONTROL 0x0060
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#define EMIF_IODFT_TEST_LOGIC_CTRL_MISR_RESULT 0x0064
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#define EMIF_IODFT_TEST_LOGIC_ADDRESS_MISR_RESULT 0x0068
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#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_1 0x006c
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#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_2 0x0070
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#define EMIF_IODFT_TEST_LOGIC_DATA_MISR_RESULT_3 0x0074
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#define EMIF_PERFORMANCE_COUNTER_1 0x0080
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#define EMIF_PERFORMANCE_COUNTER_2 0x0084
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#define EMIF_PERFORMANCE_COUNTER_CONFIG 0x0088
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#define EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT 0x008c
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#define EMIF_PERFORMANCE_COUNTER_TIME 0x0090
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#define EMIF_MISC_REG 0x0094
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#define EMIF_DLL_CALIB_CTRL 0x0098
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#define EMIF_DLL_CALIB_CTRL_SHDW 0x009c
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#define EMIF_END_OF_INTERRUPT 0x00a0
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#define EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS 0x00a4
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#define EMIF_LL_OCP_INTERRUPT_RAW_STATUS 0x00a8
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#define EMIF_SYSTEM_OCP_INTERRUPT_STATUS 0x00ac
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#define EMIF_LL_OCP_INTERRUPT_STATUS 0x00b0
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#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET 0x00b4
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#define EMIF_LL_OCP_INTERRUPT_ENABLE_SET 0x00b8
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#define EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR 0x00bc
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#define EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR 0x00c0
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#define EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG 0x00c8
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#define EMIF_TEMPERATURE_ALERT_CONFIG 0x00cc
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#define EMIF_OCP_ERROR_LOG 0x00d0
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#define EMIF_READ_WRITE_LEVELING_RAMP_WINDOW 0x00d4
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#define EMIF_READ_WRITE_LEVELING_RAMP_CONTROL 0x00d8
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#define EMIF_READ_WRITE_LEVELING_CONTROL 0x00dc
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#define EMIF_DDR_PHY_CTRL_1 0x00e4
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#define EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8
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#define EMIF_DDR_PHY_CTRL_2 0x00ec
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#define EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING 0x0100
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#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING 0x0104
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#define EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING 0x0108
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#define EMIF_READ_WRITE_EXECUTION_THRESHOLD 0x0120
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#define EMIF_COS_CONFIG 0x0124
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#define EMIF_PHY_STATUS_1 0x0140
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#define EMIF_PHY_STATUS_2 0x0144
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#define EMIF_PHY_STATUS_3 0x0148
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#define EMIF_PHY_STATUS_4 0x014c
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#define EMIF_PHY_STATUS_5 0x0150
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#define EMIF_PHY_STATUS_6 0x0154
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#define EMIF_PHY_STATUS_7 0x0158
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#define EMIF_PHY_STATUS_8 0x015c
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#define EMIF_PHY_STATUS_9 0x0160
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#define EMIF_PHY_STATUS_10 0x0164
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#define EMIF_PHY_STATUS_11 0x0168
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#define EMIF_PHY_STATUS_12 0x016c
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#define EMIF_PHY_STATUS_13 0x0170
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#define EMIF_PHY_STATUS_14 0x0174
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#define EMIF_PHY_STATUS_15 0x0178
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#define EMIF_PHY_STATUS_16 0x017c
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#define EMIF_PHY_STATUS_17 0x0180
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#define EMIF_PHY_STATUS_18 0x0184
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#define EMIF_PHY_STATUS_19 0x0188
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#define EMIF_PHY_STATUS_20 0x018c
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#define EMIF_PHY_STATUS_21 0x0190
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#define EMIF_EXT_PHY_CTRL_1 0x0200
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#define EMIF_EXT_PHY_CTRL_1_SHDW 0x0204
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#define EMIF_EXT_PHY_CTRL_2 0x0208
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#define EMIF_EXT_PHY_CTRL_2_SHDW 0x020c
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#define EMIF_EXT_PHY_CTRL_3 0x0210
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#define EMIF_EXT_PHY_CTRL_3_SHDW 0x0214
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#define EMIF_EXT_PHY_CTRL_4 0x0218
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#define EMIF_EXT_PHY_CTRL_4_SHDW 0x021c
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#define EMIF_EXT_PHY_CTRL_5 0x0220
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#define EMIF_EXT_PHY_CTRL_5_SHDW 0x0224
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#define EMIF_EXT_PHY_CTRL_6 0x0228
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#define EMIF_EXT_PHY_CTRL_6_SHDW 0x022c
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#define EMIF_EXT_PHY_CTRL_7 0x0230
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#define EMIF_EXT_PHY_CTRL_7_SHDW 0x0234
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#define EMIF_EXT_PHY_CTRL_8 0x0238
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#define EMIF_EXT_PHY_CTRL_8_SHDW 0x023c
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#define EMIF_EXT_PHY_CTRL_9 0x0240
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#define EMIF_EXT_PHY_CTRL_9_SHDW 0x0244
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#define EMIF_EXT_PHY_CTRL_10 0x0248
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#define EMIF_EXT_PHY_CTRL_10_SHDW 0x024c
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#define EMIF_EXT_PHY_CTRL_11 0x0250
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#define EMIF_EXT_PHY_CTRL_11_SHDW 0x0254
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#define EMIF_EXT_PHY_CTRL_12 0x0258
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#define EMIF_EXT_PHY_CTRL_12_SHDW 0x025c
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#define EMIF_EXT_PHY_CTRL_13 0x0260
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#define EMIF_EXT_PHY_CTRL_13_SHDW 0x0264
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#define EMIF_EXT_PHY_CTRL_14 0x0268
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#define EMIF_EXT_PHY_CTRL_14_SHDW 0x026c
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#define EMIF_EXT_PHY_CTRL_15 0x0270
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#define EMIF_EXT_PHY_CTRL_15_SHDW 0x0274
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#define EMIF_EXT_PHY_CTRL_16 0x0278
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#define EMIF_EXT_PHY_CTRL_16_SHDW 0x027c
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#define EMIF_EXT_PHY_CTRL_17 0x0280
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#define EMIF_EXT_PHY_CTRL_17_SHDW 0x0284
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#define EMIF_EXT_PHY_CTRL_18 0x0288
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#define EMIF_EXT_PHY_CTRL_18_SHDW 0x028c
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#define EMIF_EXT_PHY_CTRL_19 0x0290
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#define EMIF_EXT_PHY_CTRL_19_SHDW 0x0294
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#define EMIF_EXT_PHY_CTRL_20 0x0298
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#define EMIF_EXT_PHY_CTRL_20_SHDW 0x029c
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#define EMIF_EXT_PHY_CTRL_21 0x02a0
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#define EMIF_EXT_PHY_CTRL_21_SHDW 0x02a4
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#define EMIF_EXT_PHY_CTRL_22 0x02a8
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#define EMIF_EXT_PHY_CTRL_22_SHDW 0x02ac
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#define EMIF_EXT_PHY_CTRL_23 0x02b0
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#define EMIF_EXT_PHY_CTRL_23_SHDW 0x02b4
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#define EMIF_EXT_PHY_CTRL_24 0x02b8
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#define EMIF_EXT_PHY_CTRL_24_SHDW 0x02bc
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#define EMIF_EXT_PHY_CTRL_25 0x02c0
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#define EMIF_EXT_PHY_CTRL_25_SHDW 0x02c4
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#define EMIF_EXT_PHY_CTRL_26 0x02c8
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#define EMIF_EXT_PHY_CTRL_26_SHDW 0x02cc
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#define EMIF_EXT_PHY_CTRL_27 0x02d0
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#define EMIF_EXT_PHY_CTRL_27_SHDW 0x02d4
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#define EMIF_EXT_PHY_CTRL_28 0x02d8
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#define EMIF_EXT_PHY_CTRL_28_SHDW 0x02dc
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#define EMIF_EXT_PHY_CTRL_29 0x02e0
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#define EMIF_EXT_PHY_CTRL_29_SHDW 0x02e4
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#define EMIF_EXT_PHY_CTRL_30 0x02e8
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#define EMIF_EXT_PHY_CTRL_30_SHDW 0x02ec
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/* Registers shifts and masks */
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/* EMIF_MODULE_ID_AND_REVISION */
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#define SCHEME_SHIFT 30
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#define SCHEME_MASK (0x3 << 30)
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#define MODULE_ID_SHIFT 16
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#define MODULE_ID_MASK (0xfff << 16)
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#define RTL_VERSION_SHIFT 11
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#define RTL_VERSION_MASK (0x1f << 11)
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#define MAJOR_REVISION_SHIFT 8
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#define MAJOR_REVISION_MASK (0x7 << 8)
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#define MINOR_REVISION_SHIFT 0
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#define MINOR_REVISION_MASK (0x3f << 0)
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/* STATUS */
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#define BE_SHIFT 31
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#define BE_MASK (1 << 31)
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#define DUAL_CLK_MODE_SHIFT 30
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#define DUAL_CLK_MODE_MASK (1 << 30)
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#define FAST_INIT_SHIFT 29
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#define FAST_INIT_MASK (1 << 29)
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#define RDLVLGATETO_SHIFT 6
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#define RDLVLGATETO_MASK (1 << 6)
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#define RDLVLTO_SHIFT 5
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#define RDLVLTO_MASK (1 << 5)
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#define WRLVLTO_SHIFT 4
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#define WRLVLTO_MASK (1 << 4)
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#define PHY_DLL_READY_SHIFT 2
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#define PHY_DLL_READY_MASK (1 << 2)
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/* SDRAM_CONFIG */
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#define SDRAM_TYPE_SHIFT 29
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#define SDRAM_TYPE_MASK (0x7 << 29)
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#define IBANK_POS_SHIFT 27
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#define IBANK_POS_MASK (0x3 << 27)
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#define DDR_TERM_SHIFT 24
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#define DDR_TERM_MASK (0x7 << 24)
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#define DDR2_DDQS_SHIFT 23
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#define DDR2_DDQS_MASK (1 << 23)
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#define DYN_ODT_SHIFT 21
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#define DYN_ODT_MASK (0x3 << 21)
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#define DDR_DISABLE_DLL_SHIFT 20
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#define DDR_DISABLE_DLL_MASK (1 << 20)
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#define SDRAM_DRIVE_SHIFT 18
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#define SDRAM_DRIVE_MASK (0x3 << 18)
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#define CWL_SHIFT 16
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#define CWL_MASK (0x3 << 16)
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#define NARROW_MODE_SHIFT 14
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#define NARROW_MODE_MASK (0x3 << 14)
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#define CL_SHIFT 10
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#define CL_MASK (0xf << 10)
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#define ROWSIZE_SHIFT 7
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#define ROWSIZE_MASK (0x7 << 7)
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#define IBANK_SHIFT 4
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#define IBANK_MASK (0x7 << 4)
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#define EBANK_SHIFT 3
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#define EBANK_MASK (1 << 3)
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#define PAGESIZE_SHIFT 0
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#define PAGESIZE_MASK (0x7 << 0)
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/* SDRAM_CONFIG_2 */
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#define CS1NVMEN_SHIFT 30
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#define CS1NVMEN_MASK (1 << 30)
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#define EBANK_POS_SHIFT 27
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#define EBANK_POS_MASK (1 << 27)
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#define RDBNUM_SHIFT 4
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#define RDBNUM_MASK (0x3 << 4)
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#define RDBSIZE_SHIFT 0
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#define RDBSIZE_MASK (0x7 << 0)
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/* SDRAM_REFRESH_CONTROL */
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#define INITREF_DIS_SHIFT 31
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#define INITREF_DIS_MASK (1 << 31)
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#define SRT_SHIFT 29
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#define SRT_MASK (1 << 29)
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#define ASR_SHIFT 28
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#define ASR_MASK (1 << 28)
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#define PASR_SHIFT 24
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#define PASR_MASK (0x7 << 24)
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#define REFRESH_RATE_SHIFT 0
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#define REFRESH_RATE_MASK (0xffff << 0)
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/* SDRAM_TIMING_1 */
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#define T_RTW_SHIFT 29
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#define T_RTW_MASK (0x7 << 29)
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#define T_RP_SHIFT 25
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#define T_RP_MASK (0xf << 25)
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#define T_RCD_SHIFT 21
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#define T_RCD_MASK (0xf << 21)
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#define T_WR_SHIFT 17
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#define T_WR_MASK (0xf << 17)
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#define T_RAS_SHIFT 12
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#define T_RAS_MASK (0x1f << 12)
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#define T_RC_SHIFT 6
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#define T_RC_MASK (0x3f << 6)
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#define T_RRD_SHIFT 3
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#define T_RRD_MASK (0x7 << 3)
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#define T_WTR_SHIFT 0
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#define T_WTR_MASK (0x7 << 0)
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/* SDRAM_TIMING_2 */
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#define T_XP_SHIFT 28
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#define T_XP_MASK (0x7 << 28)
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#define T_ODT_SHIFT 25
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#define T_ODT_MASK (0x7 << 25)
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#define T_XSNR_SHIFT 16
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#define T_XSNR_MASK (0x1ff << 16)
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#define T_XSRD_SHIFT 6
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#define T_XSRD_MASK (0x3ff << 6)
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#define T_RTP_SHIFT 3
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#define T_RTP_MASK (0x7 << 3)
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#define T_CKE_SHIFT 0
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#define T_CKE_MASK (0x7 << 0)
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/* SDRAM_TIMING_3 */
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#define T_PDLL_UL_SHIFT 28
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#define T_PDLL_UL_MASK (0xf << 28)
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#define T_CSTA_SHIFT 24
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#define T_CSTA_MASK (0xf << 24)
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#define T_CKESR_SHIFT 21
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#define T_CKESR_MASK (0x7 << 21)
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#define ZQ_ZQCS_SHIFT 15
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#define ZQ_ZQCS_MASK (0x3f << 15)
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#define T_TDQSCKMAX_SHIFT 13
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#define T_TDQSCKMAX_MASK (0x3 << 13)
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#define T_RFC_SHIFT 4
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#define T_RFC_MASK (0x1ff << 4)
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#define T_RAS_MAX_SHIFT 0
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#define T_RAS_MAX_MASK (0xf << 0)
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/* POWER_MANAGEMENT_CONTROL */
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#define PD_TIM_SHIFT 12
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#define PD_TIM_MASK (0xf << 12)
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#define DPD_EN_SHIFT 11
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#define DPD_EN_MASK (1 << 11)
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#define LP_MODE_SHIFT 8
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#define LP_MODE_MASK (0x7 << 8)
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#define SR_TIM_SHIFT 4
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#define SR_TIM_MASK (0xf << 4)
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#define CS_TIM_SHIFT 0
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#define CS_TIM_MASK (0xf << 0)
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/* LPDDR2_MODE_REG_DATA */
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#define VALUE_0_SHIFT 0
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#define VALUE_0_MASK (0x7f << 0)
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/* LPDDR2_MODE_REG_CONFIG */
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#define CS_SHIFT 31
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#define CS_MASK (1 << 31)
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#define REFRESH_EN_SHIFT 30
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#define REFRESH_EN_MASK (1 << 30)
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#define ADDRESS_SHIFT 0
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#define ADDRESS_MASK (0xff << 0)
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/* OCP_CONFIG */
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#define SYS_THRESH_MAX_SHIFT 24
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#define SYS_THRESH_MAX_MASK (0xf << 24)
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#define MPU_THRESH_MAX_SHIFT 20
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#define MPU_THRESH_MAX_MASK (0xf << 20)
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#define LL_THRESH_MAX_SHIFT 16
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#define LL_THRESH_MAX_MASK (0xf << 16)
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/* PERFORMANCE_COUNTER_1 */
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#define COUNTER1_SHIFT 0
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#define COUNTER1_MASK (0xffffffff << 0)
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/* PERFORMANCE_COUNTER_2 */
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#define COUNTER2_SHIFT 0
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#define COUNTER2_MASK (0xffffffff << 0)
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/* PERFORMANCE_COUNTER_CONFIG */
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#define CNTR2_MCONNID_EN_SHIFT 31
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#define CNTR2_MCONNID_EN_MASK (1 << 31)
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#define CNTR2_REGION_EN_SHIFT 30
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#define CNTR2_REGION_EN_MASK (1 << 30)
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#define CNTR2_CFG_SHIFT 16
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#define CNTR2_CFG_MASK (0xf << 16)
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#define CNTR1_MCONNID_EN_SHIFT 15
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#define CNTR1_MCONNID_EN_MASK (1 << 15)
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#define CNTR1_REGION_EN_SHIFT 14
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#define CNTR1_REGION_EN_MASK (1 << 14)
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#define CNTR1_CFG_SHIFT 0
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#define CNTR1_CFG_MASK (0xf << 0)
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/* PERFORMANCE_COUNTER_MASTER_REGION_SELECT */
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#define MCONNID2_SHIFT 24
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#define MCONNID2_MASK (0xff << 24)
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#define REGION_SEL2_SHIFT 16
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#define REGION_SEL2_MASK (0x3 << 16)
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#define MCONNID1_SHIFT 8
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#define MCONNID1_MASK (0xff << 8)
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#define REGION_SEL1_SHIFT 0
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#define REGION_SEL1_MASK (0x3 << 0)
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/* PERFORMANCE_COUNTER_TIME */
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#define TOTAL_TIME_SHIFT 0
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#define TOTAL_TIME_MASK (0xffffffff << 0)
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|
|
|
/* DLL_CALIB_CTRL */
|
|
#define ACK_WAIT_SHIFT 16
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#define ACK_WAIT_MASK (0xf << 16)
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|
#define DLL_CALIB_INTERVAL_SHIFT 0
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#define DLL_CALIB_INTERVAL_MASK (0x1ff << 0)
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|
|
|
/* END_OF_INTERRUPT */
|
|
#define EOI_SHIFT 0
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|
#define EOI_MASK (1 << 0)
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|
|
|
/* SYSTEM_OCP_INTERRUPT_RAW_STATUS */
|
|
#define DNV_SYS_SHIFT 2
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#define DNV_SYS_MASK (1 << 2)
|
|
#define TA_SYS_SHIFT 1
|
|
#define TA_SYS_MASK (1 << 1)
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|
#define ERR_SYS_SHIFT 0
|
|
#define ERR_SYS_MASK (1 << 0)
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|
|
|
/* LOW_LATENCY_OCP_INTERRUPT_RAW_STATUS */
|
|
#define DNV_LL_SHIFT 2
|
|
#define DNV_LL_MASK (1 << 2)
|
|
#define TA_LL_SHIFT 1
|
|
#define TA_LL_MASK (1 << 1)
|
|
#define ERR_LL_SHIFT 0
|
|
#define ERR_LL_MASK (1 << 0)
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|
|
|
/* SYSTEM_OCP_INTERRUPT_ENABLE_SET */
|
|
#define EN_DNV_SYS_SHIFT 2
|
|
#define EN_DNV_SYS_MASK (1 << 2)
|
|
#define EN_TA_SYS_SHIFT 1
|
|
#define EN_TA_SYS_MASK (1 << 1)
|
|
#define EN_ERR_SYS_SHIFT 0
|
|
#define EN_ERR_SYS_MASK (1 << 0)
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|
|
|
/* LOW_LATENCY_OCP_INTERRUPT_ENABLE_SET */
|
|
#define EN_DNV_LL_SHIFT 2
|
|
#define EN_DNV_LL_MASK (1 << 2)
|
|
#define EN_TA_LL_SHIFT 1
|
|
#define EN_TA_LL_MASK (1 << 1)
|
|
#define EN_ERR_LL_SHIFT 0
|
|
#define EN_ERR_LL_MASK (1 << 0)
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|
|
|
/* SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG */
|
|
#define ZQ_CS1EN_SHIFT 31
|
|
#define ZQ_CS1EN_MASK (1 << 31)
|
|
#define ZQ_CS0EN_SHIFT 30
|
|
#define ZQ_CS0EN_MASK (1 << 30)
|
|
#define ZQ_DUALCALEN_SHIFT 29
|
|
#define ZQ_DUALCALEN_MASK (1 << 29)
|
|
#define ZQ_SFEXITEN_SHIFT 28
|
|
#define ZQ_SFEXITEN_MASK (1 << 28)
|
|
#define ZQ_ZQINIT_MULT_SHIFT 18
|
|
#define ZQ_ZQINIT_MULT_MASK (0x3 << 18)
|
|
#define ZQ_ZQCL_MULT_SHIFT 16
|
|
#define ZQ_ZQCL_MULT_MASK (0x3 << 16)
|
|
#define ZQ_REFINTERVAL_SHIFT 0
|
|
#define ZQ_REFINTERVAL_MASK (0xffff << 0)
|
|
|
|
/* TEMPERATURE_ALERT_CONFIG */
|
|
#define TA_CS1EN_SHIFT 31
|
|
#define TA_CS1EN_MASK (1 << 31)
|
|
#define TA_CS0EN_SHIFT 30
|
|
#define TA_CS0EN_MASK (1 << 30)
|
|
#define TA_SFEXITEN_SHIFT 28
|
|
#define TA_SFEXITEN_MASK (1 << 28)
|
|
#define TA_DEVWDT_SHIFT 26
|
|
#define TA_DEVWDT_MASK (0x3 << 26)
|
|
#define TA_DEVCNT_SHIFT 24
|
|
#define TA_DEVCNT_MASK (0x3 << 24)
|
|
#define TA_REFINTERVAL_SHIFT 0
|
|
#define TA_REFINTERVAL_MASK (0x3fffff << 0)
|
|
|
|
/* OCP_ERROR_LOG */
|
|
#define MADDRSPACE_SHIFT 14
|
|
#define MADDRSPACE_MASK (0x3 << 14)
|
|
#define MBURSTSEQ_SHIFT 11
|
|
#define MBURSTSEQ_MASK (0x7 << 11)
|
|
#define MCMD_SHIFT 8
|
|
#define MCMD_MASK (0x7 << 8)
|
|
#define MCONNID_SHIFT 0
|
|
#define MCONNID_MASK (0xff << 0)
|
|
|
|
/* DDR_PHY_CTRL_1 - EMIF4D */
|
|
#define DLL_SLAVE_DLY_CTRL_SHIFT_4D 4
|
|
#define DLL_SLAVE_DLY_CTRL_MASK_4D (0xFF << 4)
|
|
#define READ_LATENCY_SHIFT_4D 0
|
|
#define READ_LATENCY_MASK_4D (0xf << 0)
|
|
|
|
/* DDR_PHY_CTRL_1 - EMIF4D5 */
|
|
#define DLL_HALF_DELAY_SHIFT_4D5 21
|
|
#define DLL_HALF_DELAY_MASK_4D5 (1 << 21)
|
|
#define READ_LATENCY_SHIFT_4D5 0
|
|
#define READ_LATENCY_MASK_4D5 (0x1f << 0)
|
|
|
|
/* DDR_PHY_CTRL_1_SHDW */
|
|
#define DDR_PHY_CTRL_1_SHDW_SHIFT 5
|
|
#define DDR_PHY_CTRL_1_SHDW_MASK (0x7ffffff << 5)
|
|
#define READ_LATENCY_SHDW_SHIFT 0
|
|
#define READ_LATENCY_SHDW_MASK (0x1f << 0)
|
|
|
|
#ifndef __ASSEMBLY__
|
|
/*
|
|
* Structure containing shadow of important registers in EMIF
|
|
* The calculation function fills in this structure to be later used for
|
|
* initialisation and DVFS
|
|
*/
|
|
struct emif_regs {
|
|
u32 freq;
|
|
u32 ref_ctrl_shdw;
|
|
u32 ref_ctrl_shdw_derated;
|
|
u32 sdram_tim1_shdw;
|
|
u32 sdram_tim1_shdw_derated;
|
|
u32 sdram_tim2_shdw;
|
|
u32 sdram_tim3_shdw;
|
|
u32 sdram_tim3_shdw_derated;
|
|
u32 pwr_mgmt_ctrl_shdw;
|
|
union {
|
|
u32 read_idle_ctrl_shdw_normal;
|
|
u32 dll_calib_ctrl_shdw_normal;
|
|
};
|
|
union {
|
|
u32 read_idle_ctrl_shdw_volt_ramp;
|
|
u32 dll_calib_ctrl_shdw_volt_ramp;
|
|
};
|
|
|
|
u32 phy_ctrl_1_shdw;
|
|
u32 ext_phy_ctrl_2_shdw;
|
|
u32 ext_phy_ctrl_3_shdw;
|
|
u32 ext_phy_ctrl_4_shdw;
|
|
};
|
|
#endif /* __ASSEMBLY__ */
|
|
#endif /* __EMIF_H */
|