15d014d131
The way the hardware and firmware work is that there is one shared RX queue and IRQ for a number of different network interfaces. Due to this, we would like to process received packets for every interface in the same NAPI poll handler, so we need a pseudo-device to schedule polling on. What the driver currently does is that it always schedules polling for the first network interface in the list, and processes packets for every interface in the poll handler for that first interface -- however, this scheme breaks down if the first network interface happens to not be up, since netif_rx_schedule_prep() checks netif_running(). sky2 apparently has the same issue, and Stephen Hemminger suggested a way to work around this: create a variant of netif_rx_schedule_prep() that does not check netif_running(). I implemented this locally and called it netif_rx_schedule_prep_notup(), and it seems to work well, but it's something that probably not everyone would be happy with. The ixp2000 is an ARM CPU with a high-speed network interface in the CPU itself (full duplex 4Gb/s or 10Gb/s depending on the IXP model.) The CPU package also contains 8 or 16 (again depending on the IXP model) 'microengines', which are somewhat primitive but very fast and efficient processor cores which can be used to offload various things from the main CPU. This driver makes the high-speed network interface in the CPU visible and usable as a regular linux network device. Currently, it only supports the Radisys ENP2611 IXP board, but adding support for other board types should be fairly easy. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
272 lines
5.9 KiB
Ucode
272 lines
5.9 KiB
Ucode
/*
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* TX ucode for the Intel IXP2400 in POS-PHY mode.
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* Copyright (C) 2004, 2005 Lennert Buytenhek
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* Dedicated to Marija Kulikova.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Assumptions made in this code:
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* - The IXP2400 MSF is configured for POS-PHY mode, in a mode where
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* only one TBUF partition is used. This includes, for example,
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* 1x32 SPHY and 1x32 MPHY32, but not 4x8 SPHY or 1x32 MPHY4. (This
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* is not an exhaustive list.)
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* - The TBUF uses 64-byte mpackets.
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* - TX descriptors reside in SRAM, and have the following format:
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* struct tx_desc
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* {
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* // to uengine
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* u32 buf_phys_addr;
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* u32 pkt_length;
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* u32 channel;
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* };
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* - Packet data resides in DRAM.
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* - Packet buffer addresses are 8-byte aligned.
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* - Scratch ring 2 is tx_pending.
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* - Scratch ring 3 is tx_done, and has status condition 'full'.
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* - This code is run on all eight threads of the microengine it runs on.
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*/
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#define TX_SEQUENCE_0 0x0060
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#define TBUF_CTRL 0x1800
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#define PARTITION_SIZE 128
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#define PARTITION_THRESH 96
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.sig volatile sig1
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.sig volatile sig2
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.sig volatile sig3
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.reg @old_tx_seq_0
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.reg @mpkts_in_flight
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.reg @next_tbuf_mpacket
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.reg @buffer_handle
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.reg @buffer_start
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.reg @packet_length
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.reg @channel
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.reg @packet_offset
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.reg zero
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immed[zero, 0]
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/*
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* Skip context 0 initialisation?
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*/
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.begin
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br!=ctx[0, mpacket_tx_loop#]
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.end
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/*
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* Wait until all pending TBUF elements have been transmitted.
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*/
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.begin
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.reg read $tx
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.sig zzz
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loop_empty#:
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msf[read, $tx, zero, TX_SEQUENCE_0, 1], ctx_swap[zzz]
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alu_shf[--, --, b, $tx, >>31]
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beq[loop_empty#]
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alu[@old_tx_seq_0, --, b, $tx]
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.end
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immed[@mpkts_in_flight, 0]
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alu[@next_tbuf_mpacket, @old_tx_seq_0, and, (PARTITION_SIZE - 1)]
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immed[@buffer_handle, 0]
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/*
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* Initialise signal pipeline.
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*/
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.begin
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local_csr_wr[SAME_ME_SIGNAL, (&sig1 << 3)]
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.set_sig sig1
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local_csr_wr[SAME_ME_SIGNAL, (&sig2 << 3)]
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.set_sig sig2
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local_csr_wr[SAME_ME_SIGNAL, (&sig3 << 3)]
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.set_sig sig3
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.end
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mpacket_tx_loop#:
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.begin
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.reg tbuf_element_index
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.reg buffer_handle
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.reg sop_eop
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.reg packet_data
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.reg channel
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.reg mpacket_size
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/*
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* If there is no packet currently being transmitted,
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* dequeue the next TX descriptor, and fetch the buffer
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* address, packet length and destination channel number.
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*/
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.begin
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.reg read $stemp $stemp2 $stemp3
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.xfer_order $stemp $stemp2 $stemp3
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.sig zzz
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ctx_arb[sig1]
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alu[--, --, b, @buffer_handle]
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bne[already_got_packet#]
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tx_nobufs#:
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scratch[get, $stemp, zero, 8, 1], ctx_swap[zzz]
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alu[@buffer_handle, --, b, $stemp]
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beq[tx_nobufs#]
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sram[read, $stemp, $stemp, 0, 3], ctx_swap[zzz]
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alu[@buffer_start, --, b, $stemp]
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alu[@packet_length, --, b, $stemp2]
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beq[zero_byte_packet#]
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alu[@channel, --, b, $stemp3]
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immed[@packet_offset, 0]
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already_got_packet#:
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local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig1 << 3))]
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.end
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/*
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* Determine tbuf element index, SOP/EOP flags, mpacket
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* offset and mpacket size and cache buffer_handle and
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* channel number.
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*/
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.begin
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alu[tbuf_element_index, --, b, @next_tbuf_mpacket]
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alu[@next_tbuf_mpacket, @next_tbuf_mpacket, +, 1]
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alu[@next_tbuf_mpacket, @next_tbuf_mpacket, and,
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(PARTITION_SIZE - 1)]
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alu[buffer_handle, --, b, @buffer_handle]
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immed[@buffer_handle, 0]
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immed[sop_eop, 1]
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alu[packet_data, --, b, @packet_offset]
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bne[no_sop#]
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alu[sop_eop, sop_eop, or, 2]
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no_sop#:
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alu[packet_data, packet_data, +, @buffer_start]
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alu[channel, --, b, @channel]
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alu[mpacket_size, @packet_length, -, @packet_offset]
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alu[--, 64, -, mpacket_size]
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bhs[eop#]
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alu[@buffer_handle, --, b, buffer_handle]
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immed[mpacket_size, 64]
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alu[sop_eop, sop_eop, and, 2]
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eop#:
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alu[@packet_offset, @packet_offset, +, mpacket_size]
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.end
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/*
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* Wait until there's enough space in the TBUF.
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*/
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.begin
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.reg read $tx
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.reg temp
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.sig zzz
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ctx_arb[sig2]
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br[test_space#]
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loop_space#:
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msf[read, $tx, zero, TX_SEQUENCE_0, 1], ctx_swap[zzz]
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alu[temp, $tx, -, @old_tx_seq_0]
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alu[temp, temp, and, 0xff]
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alu[@mpkts_in_flight, @mpkts_in_flight, -, temp]
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alu[@old_tx_seq_0, --, b, $tx]
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test_space#:
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alu[--, PARTITION_THRESH, -, @mpkts_in_flight]
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blo[loop_space#]
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alu[@mpkts_in_flight, @mpkts_in_flight, +, 1]
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local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig2 << 3))]
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.end
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/*
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* Copy the packet data to the TBUF.
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*/
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.begin
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.reg temp
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.sig copy_sig
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alu[temp, mpacket_size, -, 1]
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alu_shf[temp, 0x10, or, temp, >>3]
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alu_shf[temp, 0x10, or, temp, <<21]
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alu_shf[temp, temp, or, tbuf_element_index, <<11]
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alu_shf[--, temp, or, 1, <<18]
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dram[tbuf_wr, --, packet_data, 0, max_8],
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indirect_ref, sig_done[copy_sig]
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ctx_arb[copy_sig]
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.end
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/*
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* Mark TBUF element as ready-to-be-transmitted.
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*/
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.begin
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.reg write $tsw $tsw2
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.xfer_order $tsw $tsw2
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.reg temp
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.sig zzz
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alu_shf[temp, channel, or, mpacket_size, <<24]
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alu_shf[$tsw, temp, or, sop_eop, <<8]
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immed[$tsw2, 0]
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immed[temp, TBUF_CTRL]
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alu_shf[temp, temp, or, tbuf_element_index, <<3]
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msf[write, $tsw, temp, 0, 2], ctx_swap[zzz]
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.end
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/*
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* Resynchronise.
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*/
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.begin
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ctx_arb[sig3]
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local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig3 << 3))]
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.end
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/*
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* If this was an EOP mpacket, recycle the TX buffer
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* and signal the host.
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*/
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.begin
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.reg write $stemp
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.sig zzz
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alu[--, sop_eop, and, 1]
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beq[mpacket_tx_loop#]
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tx_done_ring_full#:
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br_inp_state[SCR_Ring3_Status, tx_done_ring_full#]
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alu[$stemp, --, b, buffer_handle]
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scratch[put, $stemp, zero, 12, 1], ctx_swap[zzz]
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cap[fast_wr, 0, XSCALE_INT_A]
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br[mpacket_tx_loop#]
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.end
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.end
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zero_byte_packet#:
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halt
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