1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
297 lines
7.2 KiB
C
297 lines
7.2 KiB
C
/*
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* arch/sh64/kernel/dma.c
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*
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* DMA routines for the SH-5 DMAC.
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*
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <asm/hardware.h>
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#include <asm/dma.h>
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#include <asm/signal.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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typedef struct {
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unsigned long dev_addr;
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unsigned long mem_addr;
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unsigned int mode;
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unsigned int count;
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} dma_info_t;
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static dma_info_t dma_info[MAX_DMA_CHANNELS];
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static DEFINE_SPINLOCK(dma_spin_lock);
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/* arch/sh64/kernel/irq_intc.c */
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extern void make_intc_irq(unsigned int irq);
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/* DMAC Interrupts */
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#define DMA_IRQ_DMTE0 18
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#define DMA_IRQ_DERR 22
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#define DMAC_COMMON_BASE (dmac_base + 0x08)
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#define DMAC_SAR_BASE (dmac_base + 0x10)
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#define DMAC_DAR_BASE (dmac_base + 0x18)
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#define DMAC_COUNT_BASE (dmac_base + 0x20)
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#define DMAC_CTRL_BASE (dmac_base + 0x28)
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#define DMAC_STATUS_BASE (dmac_base + 0x30)
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#define DMAC_SAR(n) (DMAC_SAR_BASE + ((n) * 0x28))
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#define DMAC_DAR(n) (DMAC_DAR_BASE + ((n) * 0x28))
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#define DMAC_COUNT(n) (DMAC_COUNT_BASE + ((n) * 0x28))
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#define DMAC_CTRL(n) (DMAC_CTRL_BASE + ((n) * 0x28))
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#define DMAC_STATUS(n) (DMAC_STATUS_BASE + ((n) * 0x28))
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/* DMAC.COMMON Bit Definitions */
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#define DMAC_COMMON_PR 0x00000001 /* Priority */
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/* Bits 1-2 Reserved */
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#define DMAC_COMMON_ME 0x00000008 /* Master Enable */
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#define DMAC_COMMON_NMI 0x00000010 /* NMI Flag */
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/* Bits 5-6 Reserved */
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#define DMAC_COMMON_ER 0x00000780 /* Error Response */
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#define DMAC_COMMON_AAE 0x00007800 /* Address Alignment Error */
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/* Bits 15-63 Reserved */
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/* DMAC.SAR Bit Definitions */
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#define DMAC_SAR_ADDR 0xffffffff /* Source Address */
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/* DMAC.DAR Bit Definitions */
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#define DMAC_DAR_ADDR 0xffffffff /* Destination Address */
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/* DMAC.COUNT Bit Definitions */
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#define DMAC_COUNT_CNT 0xffffffff /* Transfer Count */
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/* DMAC.CTRL Bit Definitions */
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#define DMAC_CTRL_TS 0x00000007 /* Transfer Size */
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#define DMAC_CTRL_SI 0x00000018 /* Source Increment */
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#define DMAC_CTRL_DI 0x00000060 /* Destination Increment */
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#define DMAC_CTRL_RS 0x00000780 /* Resource Select */
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#define DMAC_CTRL_IE 0x00000800 /* Interrupt Enable */
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#define DMAC_CTRL_TE 0x00001000 /* Transfer Enable */
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/* Bits 15-63 Reserved */
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/* DMAC.STATUS Bit Definitions */
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#define DMAC_STATUS_TE 0x00000001 /* Transfer End */
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#define DMAC_STATUS_AAE 0x00000002 /* Address Alignment Error */
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/* Bits 2-63 Reserved */
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static unsigned long dmac_base;
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void set_dma_count(unsigned int chan, unsigned int count);
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void set_dma_addr(unsigned int chan, unsigned int addr);
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static irqreturn_t dma_mte(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned int chan = irq - DMA_IRQ_DMTE0;
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dma_info_t *info = dma_info + chan;
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u64 status;
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if (info->mode & DMA_MODE_WRITE) {
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sh64_out64(info->mem_addr & DMAC_SAR_ADDR, DMAC_SAR(chan));
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} else {
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sh64_out64(info->mem_addr & DMAC_DAR_ADDR, DMAC_DAR(chan));
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}
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set_dma_count(chan, info->count);
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/* Clear the TE bit */
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status = sh64_in64(DMAC_STATUS(chan));
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status &= ~DMAC_STATUS_TE;
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sh64_out64(status, DMAC_STATUS(chan));
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return IRQ_HANDLED;
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}
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static struct irqaction irq_dmte = {
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.handler = dma_mte,
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.flags = SA_INTERRUPT,
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.name = "DMA MTE",
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};
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static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
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{
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u64 tmp;
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u8 chan;
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printk(KERN_NOTICE "DMAC: Got a DMA Error!\n");
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tmp = sh64_in64(DMAC_COMMON_BASE);
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/* Check for the type of error */
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if ((chan = tmp & DMAC_COMMON_AAE)) {
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/* It's an address alignment error.. */
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printk(KERN_NOTICE "DMAC: Alignment error on channel %d, ", chan);
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printk(KERN_NOTICE "SAR: 0x%08llx, DAR: 0x%08llx, COUNT: %lld\n",
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(sh64_in64(DMAC_SAR(chan)) & DMAC_SAR_ADDR),
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(sh64_in64(DMAC_DAR(chan)) & DMAC_DAR_ADDR),
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(sh64_in64(DMAC_COUNT(chan)) & DMAC_COUNT_CNT));
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} else if ((chan = tmp & DMAC_COMMON_ER)) {
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/* Something else went wrong.. */
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printk(KERN_NOTICE "DMAC: Error on channel %d\n", chan);
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}
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/* Reset the ME bit to clear the interrupt */
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tmp |= DMAC_COMMON_ME;
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sh64_out64(tmp, DMAC_COMMON_BASE);
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return IRQ_HANDLED;
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}
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static struct irqaction irq_derr = {
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.handler = dma_err,
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.flags = SA_INTERRUPT,
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.name = "DMA Error",
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};
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static inline unsigned long calc_xmit_shift(unsigned int chan)
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{
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return sh64_in64(DMAC_CTRL(chan)) & 0x03;
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}
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void setup_dma(unsigned int chan, dma_info_t *info)
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{
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unsigned int irq = DMA_IRQ_DMTE0 + chan;
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dma_info_t *dma = dma_info + chan;
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make_intc_irq(irq);
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setup_irq(irq, &irq_dmte);
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dma = info;
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}
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void enable_dma(unsigned int chan)
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{
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u64 ctrl;
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ctrl = sh64_in64(DMAC_CTRL(chan));
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ctrl |= DMAC_CTRL_TE;
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sh64_out64(ctrl, DMAC_CTRL(chan));
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}
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void disable_dma(unsigned int chan)
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{
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u64 ctrl;
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ctrl = sh64_in64(DMAC_CTRL(chan));
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ctrl &= ~DMAC_CTRL_TE;
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sh64_out64(ctrl, DMAC_CTRL(chan));
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}
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void set_dma_mode(unsigned int chan, char mode)
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{
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dma_info_t *info = dma_info + chan;
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info->mode = mode;
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set_dma_addr(chan, info->mem_addr);
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set_dma_count(chan, info->count);
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}
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void set_dma_addr(unsigned int chan, unsigned int addr)
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{
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dma_info_t *info = dma_info + chan;
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unsigned long sar, dar;
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info->mem_addr = addr;
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sar = (info->mode & DMA_MODE_WRITE) ? info->mem_addr : info->dev_addr;
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dar = (info->mode & DMA_MODE_WRITE) ? info->dev_addr : info->mem_addr;
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sh64_out64(sar & DMAC_SAR_ADDR, DMAC_SAR(chan));
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sh64_out64(dar & DMAC_SAR_ADDR, DMAC_DAR(chan));
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}
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void set_dma_count(unsigned int chan, unsigned int count)
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{
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dma_info_t *info = dma_info + chan;
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u64 tmp;
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info->count = count;
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tmp = (info->count >> calc_xmit_shift(chan)) & DMAC_COUNT_CNT;
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sh64_out64(tmp, DMAC_COUNT(chan));
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}
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unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&dma_spin_lock, flags);
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return flags;
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}
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void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&dma_spin_lock, flags);
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}
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int get_dma_residue(unsigned int chan)
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{
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return sh64_in64(DMAC_COUNT(chan) << calc_xmit_shift(chan));
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}
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int __init init_dma(void)
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{
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struct vcr_info vcr;
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u64 tmp;
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/* Remap the DMAC */
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dmac_base = onchip_remap(PHYS_DMAC_BLOCK, 1024, "DMAC");
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if (!dmac_base) {
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printk(KERN_ERR "Unable to remap DMAC\n");
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return -ENOMEM;
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}
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/* Report DMAC.VCR Info */
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vcr = sh64_get_vcr_info(dmac_base);
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printk("DMAC: Module ID: 0x%04x, Module version: 0x%04x\n",
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vcr.mod_id, vcr.mod_vers);
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/* Set the ME bit */
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tmp = sh64_in64(DMAC_COMMON_BASE);
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tmp |= DMAC_COMMON_ME;
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sh64_out64(tmp, DMAC_COMMON_BASE);
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/* Enable the DMAC Error Interrupt */
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make_intc_irq(DMA_IRQ_DERR);
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setup_irq(DMA_IRQ_DERR, &irq_derr);
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return 0;
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}
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static void __exit exit_dma(void)
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{
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onchip_unmap(dmac_base);
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free_irq(DMA_IRQ_DERR, 0);
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}
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module_init(init_dma);
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module_exit(exit_dma);
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MODULE_AUTHOR("Paul Mundt");
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MODULE_DESCRIPTION("DMA API for SH-5 DMAC");
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MODULE_LICENSE("GPL");
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EXPORT_SYMBOL(setup_dma);
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EXPORT_SYMBOL(claim_dma_lock);
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EXPORT_SYMBOL(release_dma_lock);
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EXPORT_SYMBOL(enable_dma);
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EXPORT_SYMBOL(disable_dma);
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EXPORT_SYMBOL(set_dma_mode);
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EXPORT_SYMBOL(set_dma_addr);
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EXPORT_SYMBOL(set_dma_count);
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EXPORT_SYMBOL(get_dma_residue);
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