2261e0e6e3
Move parts of the core and debug suspend code into the plat-s3c for use with the new s3c64xx code. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
360 lines
8.8 KiB
C
360 lines
8.8 KiB
C
/* linux/arch/arm/plat-s3c24xx/pm.c
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*
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* Copyright (c) 2004,2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX Power Manager (Suspend-To-RAM) support
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*
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* See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Parts based on arch/arm/mach-pxa/pm.c
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*
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* Thanks to Dimitry Andric for debugging
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-irq.h>
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#include <asm/mach/time.h>
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#include <plat/pm.h>
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#define PFX "s3c24xx-pm: "
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static struct sleep_save core_save[] = {
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SAVE_ITEM(S3C2410_LOCKTIME),
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SAVE_ITEM(S3C2410_CLKCON),
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/* we restore the timings here, with the proviso that the board
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* brings the system up in an slower, or equal frequency setting
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* to the original system.
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*
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* if we cannot guarantee this, then things are going to go very
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* wrong here, as we modify the refresh and both pll settings.
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*/
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SAVE_ITEM(S3C2410_BWSCON),
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SAVE_ITEM(S3C2410_BANKCON0),
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SAVE_ITEM(S3C2410_BANKCON1),
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SAVE_ITEM(S3C2410_BANKCON2),
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SAVE_ITEM(S3C2410_BANKCON3),
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SAVE_ITEM(S3C2410_BANKCON4),
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SAVE_ITEM(S3C2410_BANKCON5),
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#ifndef CONFIG_CPU_FREQ
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SAVE_ITEM(S3C2410_CLKDIVN),
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SAVE_ITEM(S3C2410_MPLLCON),
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SAVE_ITEM(S3C2410_REFRESH),
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#endif
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SAVE_ITEM(S3C2410_UPLLCON),
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SAVE_ITEM(S3C2410_CLKSLOW),
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};
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static struct gpio_sleep {
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void __iomem *base;
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unsigned int gpcon;
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unsigned int gpdat;
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unsigned int gpup;
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} gpio_save[] = {
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[0] = {
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.base = S3C2410_GPACON,
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},
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[1] = {
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.base = S3C2410_GPBCON,
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},
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[2] = {
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.base = S3C2410_GPCCON,
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},
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[3] = {
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.base = S3C2410_GPDCON,
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},
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[4] = {
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.base = S3C2410_GPECON,
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},
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[5] = {
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.base = S3C2410_GPFCON,
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},
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[6] = {
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.base = S3C2410_GPGCON,
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},
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[7] = {
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.base = S3C2410_GPHCON,
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},
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};
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static struct sleep_save misc_save[] = {
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SAVE_ITEM(S3C2410_DCLKCON),
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};
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/* s3c_pm_check_resume_pin
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*
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* check to see if the pin is configured correctly for sleep mode, and
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* make any necessary adjustments if it is not
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*/
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static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
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{
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unsigned long irqstate;
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unsigned long pinstate;
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int irq = s3c2410_gpio_getirq(pin);
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if (irqoffs < 4)
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irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
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else
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irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
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pinstate = s3c2410_gpio_getcfg(pin);
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if (!irqstate) {
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if (pinstate == S3C2410_GPIO_IRQ)
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S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
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} else {
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if (pinstate == S3C2410_GPIO_IRQ) {
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S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
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s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
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}
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}
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}
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/* s3c_pm_configure_extint
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*
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* configure all external interrupt pins
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*/
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void s3c_pm_configure_extint(void)
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{
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int pin;
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/* for each of the external interrupts (EINT0..EINT15) we
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* need to check wether it is an external interrupt source,
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* and then configure it as an input if it is not
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*/
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for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
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s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
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}
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for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
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s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
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}
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}
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/* offsets for CON/DAT/UP registers */
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#define OFFS_CON (S3C2410_GPACON - S3C2410_GPACON)
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#define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON)
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#define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON)
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/* s3c_pm_save_gpios()
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*
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* Save the state of the GPIOs
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*/
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void s3c_pm_save_gpios(void)
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{
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struct gpio_sleep *gps = gpio_save;
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unsigned int gpio;
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for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
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void __iomem *base = gps->base;
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gps->gpcon = __raw_readl(base + OFFS_CON);
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gps->gpdat = __raw_readl(base + OFFS_DAT);
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if (gpio > 0)
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gps->gpup = __raw_readl(base + OFFS_UP);
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}
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}
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/* Test whether the given masked+shifted bits of an GPIO configuration
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* are one of the SFN (special function) modes. */
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static inline int is_sfn(unsigned long con)
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{
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return (con == 2 || con == 3);
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}
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/* Test if the given masked+shifted GPIO configuration is an input */
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static inline int is_in(unsigned long con)
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{
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return con == 0;
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}
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/* Test if the given masked+shifted GPIO configuration is an output */
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static inline int is_out(unsigned long con)
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{
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return con == 1;
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}
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/**
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* s3c2410_pm_restore_gpio() - restore the given GPIO bank
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* @index: The number of the GPIO bank being resumed.
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* @gps: The sleep confgiuration for the bank.
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*
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* Restore one of the GPIO banks that was saved during suspend. This is
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* not as simple as once thought, due to the possibility of glitches
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* from the order that the CON and DAT registers are set in.
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*
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* The three states the pin can be are {IN,OUT,SFN} which gives us 9
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* combinations of changes to check. Three of these, if the pin stays
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* in the same configuration can be discounted. This leaves us with
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* the following:
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*
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* { IN => OUT } Change DAT first
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* { IN => SFN } Change CON first
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* { OUT => SFN } Change CON first, so new data will not glitch
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* { OUT => IN } Change CON first, so new data will not glitch
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* { SFN => IN } Change CON first
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* { SFN => OUT } Change DAT first, so new data will not glitch [1]
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*
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* We do not currently deal with the UP registers as these control
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* weak resistors, so a small delay in change should not need to bring
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* these into the calculations.
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*
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* [1] this assumes that writing to a pin DAT whilst in SFN will set the
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* state for when it is next output.
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*/
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static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
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{
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void __iomem *base = gps->base;
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unsigned long gps_gpcon = gps->gpcon;
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unsigned long gps_gpdat = gps->gpdat;
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unsigned long old_gpcon;
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unsigned long old_gpdat;
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unsigned long old_gpup = 0x0;
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unsigned long gpcon;
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int nr;
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old_gpcon = __raw_readl(base + OFFS_CON);
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old_gpdat = __raw_readl(base + OFFS_DAT);
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if (base == S3C2410_GPACON) {
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/* GPACON only has one bit per control / data and no PULLUPs.
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* GPACON[x] = 0 => Output, 1 => SFN */
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/* first set all SFN bits to SFN */
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gpcon = old_gpcon | gps->gpcon;
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__raw_writel(gpcon, base + OFFS_CON);
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/* now set all the other bits */
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__raw_writel(gps_gpdat, base + OFFS_DAT);
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__raw_writel(gps_gpcon, base + OFFS_CON);
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} else {
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unsigned long old, new, mask;
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unsigned long change_mask = 0x0;
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old_gpup = __raw_readl(base + OFFS_UP);
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/* Create a change_mask of all the items that need to have
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* their CON value changed before their DAT value, so that
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* we minimise the work between the two settings.
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*/
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for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
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old = (old_gpcon & mask) >> nr;
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new = (gps_gpcon & mask) >> nr;
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/* If there is no change, then skip */
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if (old == new)
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continue;
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/* If both are special function, then skip */
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if (is_sfn(old) && is_sfn(new))
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continue;
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/* Change is IN => OUT, do not change now */
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if (is_in(old) && is_out(new))
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continue;
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/* Change is SFN => OUT, do not change now */
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if (is_sfn(old) && is_out(new))
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continue;
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/* We should now be at the case of IN=>SFN,
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* OUT=>SFN, OUT=>IN, SFN=>IN. */
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change_mask |= mask;
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}
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/* Write the new CON settings */
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gpcon = old_gpcon & ~change_mask;
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gpcon |= gps_gpcon & change_mask;
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__raw_writel(gpcon, base + OFFS_CON);
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/* Now change any items that require DAT,CON */
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__raw_writel(gps_gpdat, base + OFFS_DAT);
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__raw_writel(gps_gpcon, base + OFFS_CON);
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__raw_writel(gps->gpup, base + OFFS_UP);
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}
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S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
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index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
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}
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/** s3c2410_pm_restore_gpios()
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*
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* Restore the state of the GPIOs
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*/
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void s3c_pm_restore_gpios(void)
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{
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struct gpio_sleep *gps = gpio_save;
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int gpio;
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for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
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s3c2410_pm_restore_gpio(gpio, gps);
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}
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}
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void s3c_pm_restore_core(void)
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{
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s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
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s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
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}
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void s3c_pm_save_core(void)
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{
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s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
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s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
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}
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