195c5f9829
For registers accessed in fast path (interrupt / softirq) avoid expensive I/O address translation. These registers are directly mapped in PCI bar 0 and do not require any window checks. Signed-off-by: Amit Kumar Salecha <amit@netxen.com> Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: David S. Miller <davem@davemloft.net>
781 lines
19 KiB
C
781 lines
19 KiB
C
/*
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* Copyright (C) 2003 - 2009 NetXen, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.
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*
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* Contact Information:
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* info@netxen.com
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* NetXen Inc,
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* 18922 Forge Drive
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* Cupertino, CA 95014-0701
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*
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*/
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#include "netxen_nic_hw.h"
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#include "netxen_nic.h"
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#define NXHAL_VERSION 1
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static u32
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netxen_poll_rsp(struct netxen_adapter *adapter)
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{
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u32 rsp = NX_CDRP_RSP_OK;
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int timeout = 0;
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do {
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/* give atleast 1ms for firmware to respond */
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msleep(1);
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if (++timeout > NX_OS_CRB_RETRY_COUNT)
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return NX_CDRP_RSP_TIMEOUT;
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rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
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} while (!NX_CDRP_IS_RSP(rsp));
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return rsp;
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}
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static u32
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netxen_issue_cmd(struct netxen_adapter *adapter,
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u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
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{
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u32 rsp;
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u32 signature = 0;
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u32 rcode = NX_RCODE_SUCCESS;
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signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version);
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/* Acquire semaphore before accessing CRB */
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if (netxen_api_lock(adapter))
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return NX_RCODE_TIMEOUT;
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NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
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NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1);
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NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2);
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NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3);
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NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd));
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rsp = netxen_poll_rsp(adapter);
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if (rsp == NX_CDRP_RSP_TIMEOUT) {
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printk(KERN_ERR "%s: card response timeout.\n",
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netxen_nic_driver_name);
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rcode = NX_RCODE_TIMEOUT;
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} else if (rsp == NX_CDRP_RSP_FAIL) {
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rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
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printk(KERN_ERR "%s: failed card response code:0x%x\n",
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netxen_nic_driver_name, rcode);
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}
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/* Release semaphore */
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netxen_api_unlock(adapter);
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return rcode;
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}
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int
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nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu)
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{
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u32 rcode = NX_RCODE_SUCCESS;
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struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
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if (recv_ctx->state == NX_HOST_CTX_STATE_ACTIVE)
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rcode = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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recv_ctx->context_id,
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mtu,
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0,
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NX_CDRP_CMD_SET_MTU);
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if (rcode != NX_RCODE_SUCCESS)
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return -EIO;
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return 0;
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}
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static int
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nx_fw_cmd_create_rx_ctx(struct netxen_adapter *adapter)
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{
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void *addr;
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nx_hostrq_rx_ctx_t *prq;
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nx_cardrsp_rx_ctx_t *prsp;
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nx_hostrq_rds_ring_t *prq_rds;
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nx_hostrq_sds_ring_t *prq_sds;
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nx_cardrsp_rds_ring_t *prsp_rds;
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nx_cardrsp_sds_ring_t *prsp_sds;
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struct nx_host_rds_ring *rds_ring;
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struct nx_host_sds_ring *sds_ring;
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dma_addr_t hostrq_phys_addr, cardrsp_phys_addr;
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u64 phys_addr;
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int i, nrds_rings, nsds_rings;
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size_t rq_size, rsp_size;
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u32 cap, reg, val;
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int err;
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struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
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nrds_rings = adapter->max_rds_rings;
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nsds_rings = adapter->max_sds_rings;
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rq_size =
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SIZEOF_HOSTRQ_RX(nx_hostrq_rx_ctx_t, nrds_rings, nsds_rings);
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rsp_size =
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SIZEOF_CARDRSP_RX(nx_cardrsp_rx_ctx_t, nrds_rings, nsds_rings);
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addr = pci_alloc_consistent(adapter->pdev,
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rq_size, &hostrq_phys_addr);
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if (addr == NULL)
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return -ENOMEM;
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prq = (nx_hostrq_rx_ctx_t *)addr;
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addr = pci_alloc_consistent(adapter->pdev,
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rsp_size, &cardrsp_phys_addr);
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if (addr == NULL) {
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err = -ENOMEM;
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goto out_free_rq;
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}
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prsp = (nx_cardrsp_rx_ctx_t *)addr;
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prq->host_rsp_dma_addr = cpu_to_le64(cardrsp_phys_addr);
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cap = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN);
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cap |= (NX_CAP0_JUMBO_CONTIGUOUS | NX_CAP0_LRO_CONTIGUOUS);
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prq->capabilities[0] = cpu_to_le32(cap);
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prq->host_int_crb_mode =
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cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
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prq->host_rds_crb_mode =
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cpu_to_le32(NX_HOST_RDS_CRB_MODE_UNIQUE);
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prq->num_rds_rings = cpu_to_le16(nrds_rings);
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prq->num_sds_rings = cpu_to_le16(nsds_rings);
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prq->rds_ring_offset = cpu_to_le32(0);
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val = le32_to_cpu(prq->rds_ring_offset) +
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(sizeof(nx_hostrq_rds_ring_t) * nrds_rings);
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prq->sds_ring_offset = cpu_to_le32(val);
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prq_rds = (nx_hostrq_rds_ring_t *)(prq->data +
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le32_to_cpu(prq->rds_ring_offset));
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for (i = 0; i < nrds_rings; i++) {
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rds_ring = &recv_ctx->rds_rings[i];
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prq_rds[i].host_phys_addr = cpu_to_le64(rds_ring->phys_addr);
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prq_rds[i].ring_size = cpu_to_le32(rds_ring->num_desc);
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prq_rds[i].ring_kind = cpu_to_le32(i);
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prq_rds[i].buff_size = cpu_to_le64(rds_ring->dma_size);
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}
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prq_sds = (nx_hostrq_sds_ring_t *)(prq->data +
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le32_to_cpu(prq->sds_ring_offset));
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for (i = 0; i < nsds_rings; i++) {
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sds_ring = &recv_ctx->sds_rings[i];
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prq_sds[i].host_phys_addr = cpu_to_le64(sds_ring->phys_addr);
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prq_sds[i].ring_size = cpu_to_le32(sds_ring->num_desc);
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prq_sds[i].msi_index = cpu_to_le16(i);
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}
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phys_addr = hostrq_phys_addr;
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err = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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(u32)(phys_addr >> 32),
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(u32)(phys_addr & 0xffffffff),
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rq_size,
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NX_CDRP_CMD_CREATE_RX_CTX);
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if (err) {
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printk(KERN_WARNING
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"Failed to create rx ctx in firmware%d\n", err);
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goto out_free_rsp;
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}
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prsp_rds = ((nx_cardrsp_rds_ring_t *)
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&prsp->data[le32_to_cpu(prsp->rds_ring_offset)]);
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for (i = 0; i < le16_to_cpu(prsp->num_rds_rings); i++) {
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rds_ring = &recv_ctx->rds_rings[i];
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reg = le32_to_cpu(prsp_rds[i].host_producer_crb);
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rds_ring->crb_rcv_producer = netxen_get_ioaddr(adapter,
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NETXEN_NIC_REG(reg - 0x200));
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}
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prsp_sds = ((nx_cardrsp_sds_ring_t *)
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&prsp->data[le32_to_cpu(prsp->sds_ring_offset)]);
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for (i = 0; i < le16_to_cpu(prsp->num_sds_rings); i++) {
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sds_ring = &recv_ctx->sds_rings[i];
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reg = le32_to_cpu(prsp_sds[i].host_consumer_crb);
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sds_ring->crb_sts_consumer = netxen_get_ioaddr(adapter,
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NETXEN_NIC_REG(reg - 0x200));
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reg = le32_to_cpu(prsp_sds[i].interrupt_crb);
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sds_ring->crb_intr_mask = netxen_get_ioaddr(adapter,
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NETXEN_NIC_REG(reg - 0x200));
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}
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recv_ctx->state = le32_to_cpu(prsp->host_ctx_state);
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recv_ctx->context_id = le16_to_cpu(prsp->context_id);
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recv_ctx->virt_port = prsp->virt_port;
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out_free_rsp:
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pci_free_consistent(adapter->pdev, rsp_size, prsp, cardrsp_phys_addr);
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out_free_rq:
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pci_free_consistent(adapter->pdev, rq_size, prq, hostrq_phys_addr);
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return err;
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}
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static void
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nx_fw_cmd_destroy_rx_ctx(struct netxen_adapter *adapter)
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{
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struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
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if (netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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recv_ctx->context_id,
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NX_DESTROY_CTX_RESET,
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0,
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NX_CDRP_CMD_DESTROY_RX_CTX)) {
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printk(KERN_WARNING
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"%s: Failed to destroy rx ctx in firmware\n",
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netxen_nic_driver_name);
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}
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}
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static int
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nx_fw_cmd_create_tx_ctx(struct netxen_adapter *adapter)
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{
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nx_hostrq_tx_ctx_t *prq;
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nx_hostrq_cds_ring_t *prq_cds;
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nx_cardrsp_tx_ctx_t *prsp;
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void *rq_addr, *rsp_addr;
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size_t rq_size, rsp_size;
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u32 temp;
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int err = 0;
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u64 offset, phys_addr;
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dma_addr_t rq_phys_addr, rsp_phys_addr;
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struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
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struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
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rq_size = SIZEOF_HOSTRQ_TX(nx_hostrq_tx_ctx_t);
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rq_addr = pci_alloc_consistent(adapter->pdev,
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rq_size, &rq_phys_addr);
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if (!rq_addr)
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return -ENOMEM;
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rsp_size = SIZEOF_CARDRSP_TX(nx_cardrsp_tx_ctx_t);
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rsp_addr = pci_alloc_consistent(adapter->pdev,
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rsp_size, &rsp_phys_addr);
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if (!rsp_addr) {
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err = -ENOMEM;
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goto out_free_rq;
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}
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memset(rq_addr, 0, rq_size);
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prq = (nx_hostrq_tx_ctx_t *)rq_addr;
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memset(rsp_addr, 0, rsp_size);
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prsp = (nx_cardrsp_tx_ctx_t *)rsp_addr;
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prq->host_rsp_dma_addr = cpu_to_le64(rsp_phys_addr);
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temp = (NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN | NX_CAP0_LSO);
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prq->capabilities[0] = cpu_to_le32(temp);
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prq->host_int_crb_mode =
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cpu_to_le32(NX_HOST_INT_CRB_MODE_SHARED);
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prq->interrupt_ctl = 0;
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prq->msi_index = 0;
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prq->dummy_dma_addr = cpu_to_le64(adapter->dummy_dma.phys_addr);
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offset = recv_ctx->phys_addr + sizeof(struct netxen_ring_ctx);
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prq->cmd_cons_dma_addr = cpu_to_le64(offset);
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prq_cds = &prq->cds_ring;
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prq_cds->host_phys_addr = cpu_to_le64(tx_ring->phys_addr);
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prq_cds->ring_size = cpu_to_le32(tx_ring->num_desc);
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phys_addr = rq_phys_addr;
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err = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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(u32)(phys_addr >> 32),
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((u32)phys_addr & 0xffffffff),
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rq_size,
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NX_CDRP_CMD_CREATE_TX_CTX);
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if (err == NX_RCODE_SUCCESS) {
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temp = le32_to_cpu(prsp->cds_ring.host_producer_crb);
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tx_ring->crb_cmd_producer = netxen_get_ioaddr(adapter,
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NETXEN_NIC_REG(temp - 0x200));
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#if 0
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adapter->tx_state =
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le32_to_cpu(prsp->host_ctx_state);
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#endif
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adapter->tx_context_id =
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le16_to_cpu(prsp->context_id);
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} else {
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printk(KERN_WARNING
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"Failed to create tx ctx in firmware%d\n", err);
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err = -EIO;
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}
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pci_free_consistent(adapter->pdev, rsp_size, rsp_addr, rsp_phys_addr);
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out_free_rq:
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pci_free_consistent(adapter->pdev, rq_size, rq_addr, rq_phys_addr);
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return err;
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}
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static void
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nx_fw_cmd_destroy_tx_ctx(struct netxen_adapter *adapter)
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{
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if (netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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adapter->tx_context_id,
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NX_DESTROY_CTX_RESET,
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0,
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NX_CDRP_CMD_DESTROY_TX_CTX)) {
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printk(KERN_WARNING
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"%s: Failed to destroy tx ctx in firmware\n",
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netxen_nic_driver_name);
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}
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}
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int
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nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
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{
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u32 rcode;
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rcode = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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reg,
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0,
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0,
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NX_CDRP_CMD_READ_PHY);
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if (rcode != NX_RCODE_SUCCESS)
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return -EIO;
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return NXRD32(adapter, NX_ARG1_CRB_OFFSET);
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}
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int
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nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val)
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{
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u32 rcode;
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rcode = netxen_issue_cmd(adapter,
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adapter->ahw.pci_func,
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NXHAL_VERSION,
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reg,
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val,
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0,
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NX_CDRP_CMD_WRITE_PHY);
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if (rcode != NX_RCODE_SUCCESS)
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return -EIO;
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return 0;
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}
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static u64 ctx_addr_sig_regs[][3] = {
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{NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
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{NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
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{NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
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{NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
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};
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#define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
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#define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
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#define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
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#define lower32(x) ((u32)((x) & 0xffffffff))
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#define upper32(x) ((u32)(((u64)(x) >> 32) & 0xffffffff))
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static struct netxen_recv_crb recv_crb_registers[] = {
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/* Instance 0 */
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{
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/* crb_rcv_producer: */
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{
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NETXEN_NIC_REG(0x100),
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/* Jumbo frames */
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NETXEN_NIC_REG(0x110),
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/* LRO */
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NETXEN_NIC_REG(0x120)
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},
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/* crb_sts_consumer: */
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{
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NETXEN_NIC_REG(0x138),
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NETXEN_NIC_REG_2(0x000),
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NETXEN_NIC_REG_2(0x004),
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NETXEN_NIC_REG_2(0x008),
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},
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/* sw_int_mask */
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{
|
|
CRB_SW_INT_MASK_0,
|
|
NETXEN_NIC_REG_2(0x044),
|
|
NETXEN_NIC_REG_2(0x048),
|
|
NETXEN_NIC_REG_2(0x04c),
|
|
},
|
|
},
|
|
/* Instance 1 */
|
|
{
|
|
/* crb_rcv_producer: */
|
|
{
|
|
NETXEN_NIC_REG(0x144),
|
|
/* Jumbo frames */
|
|
NETXEN_NIC_REG(0x154),
|
|
/* LRO */
|
|
NETXEN_NIC_REG(0x164)
|
|
},
|
|
/* crb_sts_consumer: */
|
|
{
|
|
NETXEN_NIC_REG(0x17c),
|
|
NETXEN_NIC_REG_2(0x020),
|
|
NETXEN_NIC_REG_2(0x024),
|
|
NETXEN_NIC_REG_2(0x028),
|
|
},
|
|
/* sw_int_mask */
|
|
{
|
|
CRB_SW_INT_MASK_1,
|
|
NETXEN_NIC_REG_2(0x064),
|
|
NETXEN_NIC_REG_2(0x068),
|
|
NETXEN_NIC_REG_2(0x06c),
|
|
},
|
|
},
|
|
/* Instance 2 */
|
|
{
|
|
/* crb_rcv_producer: */
|
|
{
|
|
NETXEN_NIC_REG(0x1d8),
|
|
/* Jumbo frames */
|
|
NETXEN_NIC_REG(0x1f8),
|
|
/* LRO */
|
|
NETXEN_NIC_REG(0x208)
|
|
},
|
|
/* crb_sts_consumer: */
|
|
{
|
|
NETXEN_NIC_REG(0x220),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
},
|
|
/* sw_int_mask */
|
|
{
|
|
CRB_SW_INT_MASK_2,
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
},
|
|
},
|
|
/* Instance 3 */
|
|
{
|
|
/* crb_rcv_producer: */
|
|
{
|
|
NETXEN_NIC_REG(0x22c),
|
|
/* Jumbo frames */
|
|
NETXEN_NIC_REG(0x23c),
|
|
/* LRO */
|
|
NETXEN_NIC_REG(0x24c)
|
|
},
|
|
/* crb_sts_consumer: */
|
|
{
|
|
NETXEN_NIC_REG(0x264),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
},
|
|
/* sw_int_mask */
|
|
{
|
|
CRB_SW_INT_MASK_3,
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
NETXEN_NIC_REG_2(0x03c),
|
|
},
|
|
},
|
|
};
|
|
|
|
static int
|
|
netxen_init_old_ctx(struct netxen_adapter *adapter)
|
|
{
|
|
struct netxen_recv_context *recv_ctx;
|
|
struct nx_host_rds_ring *rds_ring;
|
|
struct nx_host_sds_ring *sds_ring;
|
|
struct nx_host_tx_ring *tx_ring;
|
|
int ring;
|
|
int port = adapter->portnum;
|
|
struct netxen_ring_ctx *hwctx;
|
|
u32 signature;
|
|
|
|
tx_ring = adapter->tx_ring;
|
|
recv_ctx = &adapter->recv_ctx;
|
|
hwctx = recv_ctx->hwctx;
|
|
|
|
hwctx->cmd_ring_addr = cpu_to_le64(tx_ring->phys_addr);
|
|
hwctx->cmd_ring_size = cpu_to_le32(tx_ring->num_desc);
|
|
|
|
|
|
for (ring = 0; ring < adapter->max_rds_rings; ring++) {
|
|
rds_ring = &recv_ctx->rds_rings[ring];
|
|
|
|
hwctx->rcv_rings[ring].addr =
|
|
cpu_to_le64(rds_ring->phys_addr);
|
|
hwctx->rcv_rings[ring].size =
|
|
cpu_to_le32(rds_ring->num_desc);
|
|
}
|
|
|
|
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
|
|
sds_ring = &recv_ctx->sds_rings[ring];
|
|
|
|
if (ring == 0) {
|
|
hwctx->sts_ring_addr = cpu_to_le64(sds_ring->phys_addr);
|
|
hwctx->sts_ring_size = cpu_to_le32(sds_ring->num_desc);
|
|
}
|
|
hwctx->sts_rings[ring].addr = cpu_to_le64(sds_ring->phys_addr);
|
|
hwctx->sts_rings[ring].size = cpu_to_le32(sds_ring->num_desc);
|
|
hwctx->sts_rings[ring].msi_index = cpu_to_le16(ring);
|
|
}
|
|
hwctx->sts_ring_count = cpu_to_le32(adapter->max_sds_rings);
|
|
|
|
signature = (adapter->max_sds_rings > 1) ?
|
|
NETXEN_CTX_SIGNATURE_V2 : NETXEN_CTX_SIGNATURE;
|
|
|
|
NXWR32(adapter, CRB_CTX_ADDR_REG_LO(port),
|
|
lower32(recv_ctx->phys_addr));
|
|
NXWR32(adapter, CRB_CTX_ADDR_REG_HI(port),
|
|
upper32(recv_ctx->phys_addr));
|
|
NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
|
|
signature | port);
|
|
return 0;
|
|
}
|
|
|
|
int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
|
|
{
|
|
void *addr;
|
|
int err = 0;
|
|
int ring;
|
|
struct netxen_recv_context *recv_ctx;
|
|
struct nx_host_rds_ring *rds_ring;
|
|
struct nx_host_sds_ring *sds_ring;
|
|
struct nx_host_tx_ring *tx_ring;
|
|
|
|
struct pci_dev *pdev = adapter->pdev;
|
|
struct net_device *netdev = adapter->netdev;
|
|
int port = adapter->portnum;
|
|
|
|
recv_ctx = &adapter->recv_ctx;
|
|
tx_ring = adapter->tx_ring;
|
|
|
|
addr = pci_alloc_consistent(pdev,
|
|
sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
|
|
&recv_ctx->phys_addr);
|
|
if (addr == NULL) {
|
|
dev_err(&pdev->dev, "failed to allocate hw context\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memset(addr, 0, sizeof(struct netxen_ring_ctx));
|
|
recv_ctx->hwctx = (struct netxen_ring_ctx *)addr;
|
|
recv_ctx->hwctx->ctx_id = cpu_to_le32(port);
|
|
recv_ctx->hwctx->cmd_consumer_offset =
|
|
cpu_to_le64(recv_ctx->phys_addr +
|
|
sizeof(struct netxen_ring_ctx));
|
|
tx_ring->hw_consumer =
|
|
(__le32 *)(((char *)addr) + sizeof(struct netxen_ring_ctx));
|
|
|
|
/* cmd desc ring */
|
|
addr = pci_alloc_consistent(pdev, TX_DESC_RINGSIZE(tx_ring),
|
|
&tx_ring->phys_addr);
|
|
|
|
if (addr == NULL) {
|
|
dev_err(&pdev->dev, "%s: failed to allocate tx desc ring\n",
|
|
netdev->name);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
tx_ring->desc_head = (struct cmd_desc_type0 *)addr;
|
|
|
|
for (ring = 0; ring < adapter->max_rds_rings; ring++) {
|
|
rds_ring = &recv_ctx->rds_rings[ring];
|
|
addr = pci_alloc_consistent(adapter->pdev,
|
|
RCV_DESC_RINGSIZE(rds_ring),
|
|
&rds_ring->phys_addr);
|
|
if (addr == NULL) {
|
|
dev_err(&pdev->dev,
|
|
"%s: failed to allocate rds ring [%d]\n",
|
|
netdev->name, ring);
|
|
err = -ENOMEM;
|
|
goto err_out_free;
|
|
}
|
|
rds_ring->desc_head = (struct rcv_desc *)addr;
|
|
|
|
if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
|
|
rds_ring->crb_rcv_producer =
|
|
netxen_get_ioaddr(adapter,
|
|
recv_crb_registers[port].crb_rcv_producer[ring]);
|
|
}
|
|
|
|
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
|
|
sds_ring = &recv_ctx->sds_rings[ring];
|
|
|
|
addr = pci_alloc_consistent(adapter->pdev,
|
|
STATUS_DESC_RINGSIZE(sds_ring),
|
|
&sds_ring->phys_addr);
|
|
if (addr == NULL) {
|
|
dev_err(&pdev->dev,
|
|
"%s: failed to allocate sds ring [%d]\n",
|
|
netdev->name, ring);
|
|
err = -ENOMEM;
|
|
goto err_out_free;
|
|
}
|
|
sds_ring->desc_head = (struct status_desc *)addr;
|
|
|
|
sds_ring->crb_sts_consumer =
|
|
netxen_get_ioaddr(adapter,
|
|
recv_crb_registers[port].crb_sts_consumer[ring]);
|
|
|
|
sds_ring->crb_intr_mask =
|
|
netxen_get_ioaddr(adapter,
|
|
recv_crb_registers[port].sw_int_mask[ring]);
|
|
}
|
|
|
|
|
|
if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
|
|
if (test_and_set_bit(__NX_FW_ATTACHED, &adapter->state))
|
|
goto done;
|
|
|
|
err = nx_fw_cmd_create_rx_ctx(adapter);
|
|
if (err)
|
|
goto err_out_free;
|
|
err = nx_fw_cmd_create_tx_ctx(adapter);
|
|
if (err)
|
|
goto err_out_free;
|
|
} else {
|
|
err = netxen_init_old_ctx(adapter);
|
|
if (err)
|
|
goto err_out_free;
|
|
}
|
|
|
|
done:
|
|
return 0;
|
|
|
|
err_out_free:
|
|
netxen_free_hw_resources(adapter);
|
|
return err;
|
|
}
|
|
|
|
void netxen_free_hw_resources(struct netxen_adapter *adapter)
|
|
{
|
|
struct netxen_recv_context *recv_ctx;
|
|
struct nx_host_rds_ring *rds_ring;
|
|
struct nx_host_sds_ring *sds_ring;
|
|
struct nx_host_tx_ring *tx_ring;
|
|
int ring;
|
|
|
|
int port = adapter->portnum;
|
|
|
|
if (!NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
|
|
if (!test_and_clear_bit(__NX_FW_ATTACHED, &adapter->state))
|
|
goto done;
|
|
|
|
nx_fw_cmd_destroy_rx_ctx(adapter);
|
|
nx_fw_cmd_destroy_tx_ctx(adapter);
|
|
} else {
|
|
netxen_api_lock(adapter);
|
|
NXWR32(adapter, CRB_CTX_SIGNATURE_REG(port),
|
|
NETXEN_CTX_D3_RESET | port);
|
|
netxen_api_unlock(adapter);
|
|
}
|
|
|
|
/* Allow dma queues to drain after context reset */
|
|
msleep(20);
|
|
|
|
done:
|
|
recv_ctx = &adapter->recv_ctx;
|
|
|
|
if (recv_ctx->hwctx != NULL) {
|
|
pci_free_consistent(adapter->pdev,
|
|
sizeof(struct netxen_ring_ctx) +
|
|
sizeof(uint32_t),
|
|
recv_ctx->hwctx,
|
|
recv_ctx->phys_addr);
|
|
recv_ctx->hwctx = NULL;
|
|
}
|
|
|
|
tx_ring = adapter->tx_ring;
|
|
if (tx_ring->desc_head != NULL) {
|
|
pci_free_consistent(adapter->pdev,
|
|
TX_DESC_RINGSIZE(tx_ring),
|
|
tx_ring->desc_head, tx_ring->phys_addr);
|
|
tx_ring->desc_head = NULL;
|
|
}
|
|
|
|
for (ring = 0; ring < adapter->max_rds_rings; ring++) {
|
|
rds_ring = &recv_ctx->rds_rings[ring];
|
|
|
|
if (rds_ring->desc_head != NULL) {
|
|
pci_free_consistent(adapter->pdev,
|
|
RCV_DESC_RINGSIZE(rds_ring),
|
|
rds_ring->desc_head,
|
|
rds_ring->phys_addr);
|
|
rds_ring->desc_head = NULL;
|
|
}
|
|
}
|
|
|
|
for (ring = 0; ring < adapter->max_sds_rings; ring++) {
|
|
sds_ring = &recv_ctx->sds_rings[ring];
|
|
|
|
if (sds_ring->desc_head != NULL) {
|
|
pci_free_consistent(adapter->pdev,
|
|
STATUS_DESC_RINGSIZE(sds_ring),
|
|
sds_ring->desc_head,
|
|
sds_ring->phys_addr);
|
|
sds_ring->desc_head = NULL;
|
|
}
|
|
}
|
|
}
|
|
|