5ce17b18e1
Fix 44x early serial debugging for big RAM configurations (more than 512M). We cannot use default OpenBIOS virtual mapping, because it interferes with pinned TLB entry. While we are at it, move early UART mapping to TLB slot 0, so it can survive longer during boot process (slot 1 is used by the first ioremap call, effectively killing UART mapping if it occupies this slot). Also, change UART TLB entry size to 4K (256M is too much for a bunch of registers :). Squash some warnings on the way. Tested on Ebony and Ocotea with 1G of RAM. Thanks to Scott Coulter <scott.coulter@cyclone.com> for diagnosing this problem. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
100 lines
2.9 KiB
C
100 lines
2.9 KiB
C
/*
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* arch/ppc/platforms/ebony.h
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*
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* Ebony board definitions
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*
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* Matt Porter <mporter@mvista.com>
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*
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* Copyright 2002 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_EBONY_H__
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#define __ASM_EBONY_H__
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#include <linux/config.h>
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#include <platforms/4xx/ibm440gp.h>
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/* F/W TLB mapping used in bootloader glue to reset EMAC */
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#define PPC44x_EMAC0_MR0 0xE0000800
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/* Where to find the MAC info */
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#define EBONY_OPENBIOS_MAC_BASE 0xfffffe0c
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#define EBONY_OPENBIOS_MAC_OFFSET 0x0c
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/* Default clock rates for Rev. B and Rev. C silicon */
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#define EBONY_440GP_RB_SYSCLK 33000000
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#define EBONY_440GP_RC_SYSCLK 400000000
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/* RTC/NVRAM location */
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#define EBONY_RTC_ADDR 0x0000000148000000ULL
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#define EBONY_RTC_SIZE 0x2000
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/* Flash */
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#define EBONY_FPGA_ADDR 0x0000000148300000ULL
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#define EBONY_BOOT_SMALL_FLASH(x) (x & 0x20)
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#define EBONY_ONBRD_FLASH_EN(x) (x & 0x02)
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#define EBONY_FLASH_SEL(x) (x & 0x01)
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#define EBONY_SMALL_FLASH_LOW1 0x00000001ff800000ULL
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#define EBONY_SMALL_FLASH_LOW2 0x00000001ff880000ULL
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#define EBONY_SMALL_FLASH_HIGH1 0x00000001fff00000ULL
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#define EBONY_SMALL_FLASH_HIGH2 0x00000001fff80000ULL
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#define EBONY_SMALL_FLASH_SIZE 0x80000
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#define EBONY_LARGE_FLASH_LOW 0x00000001ff800000ULL
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#define EBONY_LARGE_FLASH_HIGH 0x00000001ffc00000ULL
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#define EBONY_LARGE_FLASH_SIZE 0x400000
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#define EBONY_SMALL_FLASH_BASE 0x00000001fff80000ULL
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#define EBONY_LARGE_FLASH_BASE 0x00000001ff800000ULL
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/*
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* Serial port defines
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*/
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#if defined(__BOOTER__)
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/* OpenBIOS defined UART mappings, used by bootloader shim */
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#define UART0_IO_BASE 0xE0000200
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#define UART1_IO_BASE 0xE0000300
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#else
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/* head_44x.S created UART mapping, used before early_serial_setup.
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* We cannot use default OpenBIOS UART mappings because they
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* don't work for configurations with more than 512M RAM. --ebs
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*/
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#define UART0_IO_BASE 0xF0000200
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#define UART1_IO_BASE 0xF0000300
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#endif
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/* external Epson SG-615P */
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#define BASE_BAUD 691200
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#define STD_UART_OP(num) \
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{ 0, BASE_BAUD, 0, UART##num##_INT, \
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(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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iomem_base: (void*)UART##num##_IO_BASE, \
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io_type: SERIAL_IO_MEM},
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(0) \
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STD_UART_OP(1)
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/* PCI support */
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#define EBONY_PCI_LOWER_IO 0x00000000
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#define EBONY_PCI_UPPER_IO 0x0000ffff
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#define EBONY_PCI_LOWER_MEM 0x80002000
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#define EBONY_PCI_UPPER_MEM 0xffffefff
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#define EBONY_PCI_CFGREGS_BASE 0x000000020ec00000
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#define EBONY_PCI_CFGA_PLB32 0x0ec00000
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#define EBONY_PCI_CFGD_PLB32 0x0ec00004
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#define EBONY_PCI_IO_BASE 0x0000000208000000ULL
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#define EBONY_PCI_IO_SIZE 0x00010000
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#define EBONY_PCI_MEM_OFFSET 0x00000000
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#endif /* __ASM_EBONY_H__ */
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#endif /* __KERNEL__ */
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