kernel-fxtec-pro1x/drivers/clk/spear/clk.c
Viresh Kumar 55b8fd4f42 SPEAr: clk: Add VCO-PLL Synthesizer clock
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations

- In normal mode
  vco = (2 * M[15:8] * Fin)/N

- In Dithered mode
  vco = (2 * M[15:0] * Fin)/(256 * N)

pll_rate = vco/2^p

vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.

This patch adds in support for this type of clock.

Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
2012-05-12 21:19:23 +02:00

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/*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*
* SPEAr clk - Common routines
*/
#include <linux/clk-provider.h>
#include <linux/types.h>
#include "clk.h"
long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
int *index)
{
unsigned long prev_rate, rate = 0;
for (*index = 0; *index < rtbl_cnt; (*index)++) {
prev_rate = rate;
rate = calc_rate(hw, parent_rate, *index);
if (drate < rate) {
/* previous clock was best */
if (*index) {
rate = prev_rate;
(*index)--;
}
break;
}
}
return rate;
}