1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/debug.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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static struct resource extpci_io_resource = {
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"pci IO space",
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0x1000, /* leave some room for ISA bus */
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DDB_PCI_IO_SIZE - 1,
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IORESOURCE_IO
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};
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static struct resource extpci_mem_resource = {
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"pci memory space",
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DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
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DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
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IORESOURCE_MEM
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};
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extern struct pci_ops ddb5476_ext_pci_ops;
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struct pci_controller ddb5476_controller = {
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.pci_ops = &ddb5476_ext_pci_ops,
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.io_resource = &extpci_io_resource,
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.mem_resource = &extpci_mem_resource
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};
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/*
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* we fix up irqs based on the slot number.
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* The first entry is at AD:11.
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*
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* This does not work for devices on sub-buses yet.
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*/
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/*
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* temporary
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*/
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#define PCI_EXT_INTA 8
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#define PCI_EXT_INTB 9
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#define PCI_EXT_INTC 10
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#define PCI_EXT_INTD 11
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#define PCI_EXT_INTE 12
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/*
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* based on ddb5477 manual page 11
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*/
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#define MAX_SLOT_NUM 21
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static unsigned char irq_map[MAX_SLOT_NUM] = {
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[ 2] = 9, /* AD:13 USB */
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[ 3] = 10, /* AD:14 PMU */
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[ 5] = 0, /* AD:16 P2P bridge */
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[ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */
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[ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */
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[ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */
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[ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */
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[13] = 14, /* AD:24 HD controller, M5229 */
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};
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int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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return irq_map[slot];
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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void __init ddb_pci_reset_bus(void)
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{
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u32 temp;
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/*
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* I am not sure about the "official" procedure, the following
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* steps work as far as I know:
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* We first set PCI cold reset bit (bit 31) in PCICTRL-H.
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* Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
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* The same is true for both PCI channels.
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*/
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temp = ddb_in32(DDB_PCICTRL + 4);
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temp |= 0x80000000;
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ddb_out32(DDB_PCICTRL + 4, temp);
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temp &= ~0xc0000000;
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ddb_out32(DDB_PCICTRL + 4, temp);
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}
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