1002148899
dw_apb_timer_init used to search the devicetree for matching timer devices, making calls to it from board files necessary. Change the dw_apb_timer_init to work with CLOCKSOURCE_OF_DECLARE. With this change the function gets called once for each timer node and tracks these number of calls to attach clockevent and clocksource devices to the nodes. Also remove the calls to dw_apb_timer_init from all previous users, as clocksource_of_init is the default for init_time now. Tested on the upcoming rk3066 code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Dinh Nguyen <dinguyen@altera.com>
125 lines
3.2 KiB
C
125 lines
3.2 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "core.h"
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void __iomem *socfpga_scu_base_addr = ((void __iomem *)(SOCFPGA_SCU_VIRT_BASE));
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void __iomem *sys_manager_base_addr;
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void __iomem *rst_manager_base_addr;
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void __iomem *clk_mgr_base_addr;
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unsigned long cpu1start_addr;
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static struct map_desc scu_io_desc __initdata = {
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.virtual = SOCFPGA_SCU_VIRT_BASE,
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.pfn = 0, /* run-time */
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.length = SZ_8K,
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.type = MT_DEVICE,
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};
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static struct map_desc uart_io_desc __initdata = {
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.virtual = 0xfec02000,
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.pfn = __phys_to_pfn(0xffc02000),
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.length = SZ_8K,
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.type = MT_DEVICE,
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};
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static void __init socfpga_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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}
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static void __init socfpga_map_io(void)
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{
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socfpga_scu_map_io();
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iotable_init(&uart_io_desc, 1);
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early_printk("Early printk initialized\n");
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}
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void __init socfpga_sysmgr_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
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if (of_property_read_u32(np, "cpu1-start-addr",
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(u32 *) &cpu1start_addr))
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pr_err("SMP: Need cpu1-start-addr in device tree.\n");
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sys_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
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rst_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr");
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clk_mgr_base_addr = of_iomap(np, 0);
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}
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static void __init socfpga_init_irq(void)
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{
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irqchip_init();
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socfpga_sysmgr_init();
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}
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static void socfpga_cyclone5_restart(char mode, const char *cmd)
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{
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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if (mode == 'h')
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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}
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static void __init socfpga_cyclone5_init(void)
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{
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l2x0_of_init(0, ~0UL);
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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of_clk_init(NULL);
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socfpga_init_clocks();
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}
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static const char *altera_dt_match[] = {
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"altr,socfpga",
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NULL
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};
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DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
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.smp = smp_ops(socfpga_smp_ops),
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.map_io = socfpga_map_io,
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.init_irq = socfpga_init_irq,
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.init_machine = socfpga_cyclone5_init,
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.restart = socfpga_cyclone5_restart,
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.dt_compat = altera_dt_match,
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MACHINE_END
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