8d20a541b0
Patches to support SMP. * Each CPU has its own current_pgd. * flush_tlb_range is implemented as flush_tlb_mm. * Atomic operations implemented with spinlocks. * Semaphores implemented with spinlocks. Signed-off-by: Mikael Starvik <starvik@axis.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
264 lines
9 KiB
C
264 lines
9 KiB
C
/*
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* linux/arch/cris/arch-v10/mm/init.c
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*
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*/
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#include <linux/config.h>
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#include <linux/mmzone.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/arch/svinto.h>
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extern void tlb_init(void);
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/*
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* The kernel is already mapped with a kernel segment at kseg_c so
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* we don't need to map it with a page table. However head.S also
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* temporarily mapped it at kseg_4 so we should set up the ksegs again,
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* clear the TLB and do some other paging setup stuff.
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*/
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void __init
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paging_init(void)
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{
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int i;
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unsigned long zones_size[MAX_NR_ZONES];
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printk("Setting up paging and the MMU.\n");
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/* clear out the init_mm.pgd that will contain the kernel's mappings */
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for(i = 0; i < PTRS_PER_PGD; i++)
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swapper_pg_dir[i] = __pgd(0);
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/* make sure the current pgd table points to something sane
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* (even if it is most probably not used until the next
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* switch_mm)
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*/
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per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
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/* initialise the TLB (tlb.c) */
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tlb_init();
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/* see README.mm for details on the KSEG setup */
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#ifdef CONFIG_CRIS_LOW_MAP
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/* Etrax-100 LX version 1 has a bug so that we cannot map anything
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* across the 0x80000000 boundary, so we need to shrink the user-virtual
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* area to 0x50000000 instead of 0xb0000000 and map things slightly
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* different. The unused areas are marked as paged so that we can catch
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* freak kernel accesses there.
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*
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* The ARTPEC chip is mapped at 0xa so we pass that segment straight
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* through. We cannot vremap it because the vmalloc area is below 0x8
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* and Juliette needs an uncached area above 0x8.
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*
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* Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards.
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* We map them straight over in LOW_MAP, but use vremap in LX version 2.
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*/
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#define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
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*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
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IO_STATE(R_MMU_KSEG, seg_e, page ) |
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IO_STATE(R_MMU_KSEG, seg_d, page ) |
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IO_STATE(R_MMU_KSEG, seg_c, page ) |
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IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
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#ifdef CONFIG_JULIETTE
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IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */
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#else
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IO_STATE(R_MMU_KSEG, seg_a, page ) |
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#endif
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IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
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IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
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IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
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IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */
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IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */
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IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
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*R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
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#ifdef CONFIG_JULIETTE
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0xa ) |
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#else
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
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#endif
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IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
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*R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
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#else
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/* This code is for the corrected Etrax-100 LX version 2... */
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#define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
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*R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */
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IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */
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IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
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IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */
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IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
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IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */
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IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
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IO_STATE(R_MMU_KSEG, seg_8, page ) |
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IO_STATE(R_MMU_KSEG, seg_7, page ) |
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IO_STATE(R_MMU_KSEG, seg_6, page ) |
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IO_STATE(R_MMU_KSEG, seg_5, page ) |
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IO_STATE(R_MMU_KSEG, seg_4, page ) |
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IO_STATE(R_MMU_KSEG, seg_3, page ) |
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IO_STATE(R_MMU_KSEG, seg_2, page ) |
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IO_STATE(R_MMU_KSEG, seg_1, page ) |
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IO_STATE(R_MMU_KSEG, seg_0, page ) );
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*R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
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IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
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*R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
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IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
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#endif
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*R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) );
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/* The MMU has been enabled ever since head.S but just to make
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* it totally obvious we do it here as well.
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*/
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*R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) |
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IO_STATE(R_MMU_CTRL, acc_excp, enable ) |
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IO_STATE(R_MMU_CTRL, we_excp, enable ) );
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*R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable);
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/*
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* initialize the bad page table and bad page to point
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* to a couple of allocated pages
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*/
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empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
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memset((void *)empty_zero_page, 0, PAGE_SIZE);
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/* All pages are DMA'able in Etrax, so put all in the DMA'able zone */
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zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
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for (i = 1; i < MAX_NR_ZONES; i++)
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zones_size[i] = 0;
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/* Use free_area_init_node instead of free_area_init, because the former
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* is designed for systems where the DRAM starts at an address substantially
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* higher than 0, like us (we start at PAGE_OFFSET). This saves space in the
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* mem_map page array.
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*/
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free_area_init_node(0, &contig_page_data, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
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}
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/* Initialize remaps of some I/O-ports. It is important that this
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* is called before any driver is initialized.
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*/
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static int
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__init init_ioremap(void)
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{
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/* Give the external I/O-port addresses their values */
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#ifdef CONFIG_CRIS_LOW_MAP
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/* Simply a linear map (see the KSEG map above in paging_init) */
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port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START |
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MEM_NON_CACHEABLE);
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port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START |
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MEM_NON_CACHEABLE);
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port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START |
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MEM_NON_CACHEABLE);
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#else
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/* Note that nothing blows up just because we do this remapping
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* it's ok even if the ports are not used or connected
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* to anything (or connected to a non-I/O thing) */
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port_cse1_addr = (volatile unsigned long *)
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ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16);
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port_csp0_addr = (volatile unsigned long *)
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ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16);
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port_csp4_addr = (volatile unsigned long *)
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ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16);
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#endif
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return 0;
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}
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__initcall(init_ioremap);
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/* Helper function for the two below */
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static inline void
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flush_etrax_cacherange(void *startadr, int length)
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{
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/* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
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* we can use to get fast dummy-reads of cachelines
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*/
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volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
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CACHED_BOOTROM);
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length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */
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while(length > 0) {
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*flushadr; /* dummy read to flush */
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flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */
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length -= 32;
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}
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}
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/* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
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* will occationally corrupt certain CPU writes if the DMA buffers
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* happen to be hot in the cache.
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*
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* As a workaround, we have to flush the relevant parts of the cache
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* before (re) inserting any receiving descriptor into the DMA HW.
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*/
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void
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prepare_rx_descriptor(struct etrax_dma_descr *desc)
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{
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flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
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}
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/* Do the same thing but flush the entire cache */
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void
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flush_etrax_cache(void)
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{
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flush_etrax_cacherange(0, 8192);
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}
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