190 lines
4.3 KiB
C
190 lines
4.3 KiB
C
/*
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* linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/localtimer.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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#include <mach/ct-ca9x4.h>
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#include <mach/motherboard.h>
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#define V2M_PA_CS7 0x10000000
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#include "core.h"
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extern void vexpress_secondary_startup(void);
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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static void __iomem *scu_base_addr(void)
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{
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return MMIO_P2V(A9_MPCORE_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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trace_hardirqs_off();
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, gic_cpu_base_addr);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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pen_release = -1;
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smp_wmb();
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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* CPUs in the holding pen until we're ready for them. However,
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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pen_release = cpu;
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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/* sanity check */
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if (ncores == 0) {
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printk(KERN_ERR
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"vexpress: strange CM count of 0? Default to 1\n");
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ncores = 1;
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}
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if (ncores > NR_CPUS) {
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printk(KERN_WARNING
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"vexpress: no. of cores (%d) greater than configured "
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"maximum of %d - clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned int ncores = num_possible_cpus();
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unsigned int cpu = smp_processor_id();
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int i;
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smp_store_cpu_info(cpu);
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/*
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* are we trying to boot more cores than exist?
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*/
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if (max_cpus > ncores)
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max_cpus = ncores;
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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/*
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* Initialise the SCU if there are more than one CPU and let
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* them know where to start.
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*/
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if (max_cpus > 1) {
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/*
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* Enable the local timer or broadcast device for the
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* boot CPU, but only if we have more than one CPU.
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*/
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percpu_timer_setup();
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scu_enable(scu_base_addr());
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/*
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* Write the address of secondary startup into the
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* system-wide flags register. The boot monitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
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writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
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MMIO_P2V(V2M_SYS_FLAGSSET));
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}
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}
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