4bedea9454
The attached patches provides part 2 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
246 lines
4.6 KiB
ArmAsm
246 lines
4.6 KiB
ArmAsm
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#define _ASMLANGUAGE
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#include <xtensa/config/specreg.h>
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#include <xtensa/config/core.h>
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#include <xtensa/cacheasm.h>
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/*
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* RB-Data: RedBoot data/bss
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* P: Boot-Parameters
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* L: Kernel-Loader
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*
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* The Linux-Kernel image including the loader must be loaded
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* to a position so that the kernel and the boot parameters
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* can fit in the space before the load address.
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* ______________________________________________________
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* |_RB-Data_|_P_|__________|_L_|___Linux-Kernel___|______|
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* ^
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* ^ Load address
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* ______________________________________________________
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* |___Linux-Kernel___|_P_|_L_|___________________________|
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*
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* The loader copies the parameter to the position that will
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* be the end of the kernel and itself to the end of the
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* parameter list.
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*/
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/* Make sure we have enough space for the 'uncompressor' */
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#define STACK_SIZE 32768
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#define HEAP_SIZE (131072*4)
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# a2: Parameter list
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# a3: Size of parameter list
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.section .start, "ax"
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.globl __start
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/* this must be the first byte of the loader! */
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__start:
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entry sp, 32 # we do not intend to return
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_call0 _start
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__start_a0:
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.align 4
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.section .text, "ax"
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.begin literal_prefix .text
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/* put literals in here! */
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.globl _start
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_start:
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/* 'reset' window registers */
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movi a4, 1
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wsr a4, PS
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rsync
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rsr a5, WINDOWBASE
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ssl a5
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sll a4, a4
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wsr a4, WINDOWSTART
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rsync
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movi a4, 0x00040000
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wsr a4, PS
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rsync
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/* copy the loader to its address
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* Note: The loader itself is a very small piece, so we assume we
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* don't partially overlap. We also assume (even more important)
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* that the kernel image is out of the way. Usually, when the
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* load address of this image is not at an arbitrary address,
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* but aligned to some 10K's we shouldn't overlap.
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*/
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/* Note: The assembler cannot relax "addi a0, a0, ..." to an
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l32r, so we load to a4 first. */
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addi a4, a0, __start - __start_a0
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mov a0, a4
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movi a4, __start
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movi a5, __reloc_end
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# a0: address where this code has been loaded
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# a4: compiled address of __start
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# a5: compiled end address
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mov.n a7, a0
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mov.n a8, a4
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1:
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l32i a10, a7, 0
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l32i a11, a7, 4
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s32i a10, a8, 0
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s32i a11, a8, 4
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l32i a10, a7, 8
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l32i a11, a7, 12
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s32i a10, a8, 8
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s32i a11, a8, 12
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addi a8, a8, 16
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addi a7, a7, 16
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blt a8, a5, 1b
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/* We have to flush and invalidate the caches here before we jump. */
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#if XCHAL_DCACHE_IS_WRITEBACK
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dcache_writeback_all a5, a6
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#endif
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icache_invalidate_all a5, a6
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movi a11, _reloc
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jx a11
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.globl _reloc
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_reloc:
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/* RedBoot is now at the end of the memory, so we don't have
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* to copy the parameter list. Keep the code around; in case
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* we need it again. */
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#if 0
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# a0: load address
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# a2: start address of parameter list
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# a3: length of parameter list
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# a4: __start
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/* copy the parameter list out of the way */
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movi a6, _param_start
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add a3, a2, a3
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2:
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l32i a8, a2, 0
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s32i a8, a6, 0
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addi a2, a2, 4
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addi a6, a6, 4
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blt a2, a3, 2b
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#endif
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/* clear BSS section */
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movi a6, __bss_start
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movi a7, __bss_end
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movi.n a5, 0
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3:
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s32i a5, a6, 0
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addi a6, a6, 4
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blt a6, a7, 3b
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movi a5, -16
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movi a1, _stack + STACK_SIZE
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and a1, a1, a5
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/* Uncompress the kernel */
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# a0: load address
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# a2: boot parameter
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# a4: __start
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movi a3, __image_load
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sub a4, a3, a4
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add a8, a0, a4
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# a1 Stack
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# a8(a4) Load address of the image
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movi a6, _image_start
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movi a10, _image_end
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movi a7, 0x1000000
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sub a11, a10, a6
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movi a9, complen
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s32i a11, a9, 0
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movi a0, 0
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# a6 destination
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# a7 maximum size of destination
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# a8 source
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# a9 ptr to length
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.extern gunzip
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movi a4, gunzip
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beqz a4, 1f
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callx4 a4
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j 2f
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# a6 destination start
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# a7 maximum size of destination
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# a8 source start
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# a9 ptr to length
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# a10 destination end
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1:
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l32i a9, a8, 0
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l32i a11, a8, 4
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s32i a9, a6, 0
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s32i a11, a6, 4
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l32i a9, a8, 8
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l32i a11, a8, 12
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s32i a9, a6, 8
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s32i a11, a6, 12
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addi a6, a6, 16
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addi a8, a8, 16
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blt a6, a10, 1b
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/* jump to the kernel */
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2:
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#if XCHAL_DCACHE_IS_WRITEBACK
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dcache_writeback_all a5, a6
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#endif
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icache_invalidate_all a5, a6
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movi a5, __start
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movi a3, boot_initrd_start
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movi a4, boot_initrd_end
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sub a3, a3, a5
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sub a4, a4, a5
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add a3, a0, a3
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add a4, a0, a4
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# a2 Boot parameter list
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# a3 initrd_start (virtual load address)
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# a4 initrd_end (virtual load address)
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movi a0, _image_start
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jx a0
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.align 16
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.data
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.globl avail_ram
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avail_ram:
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.long _heap
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.globl end_avail
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end_avail:
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.long _heap + HEAP_SIZE
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.comm _stack, STACK_SIZE
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.comm _heap, HEAP_SIZE
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.globl end_avail
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.comm complen, 4
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.end literal_prefix
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