6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
157 lines
3.9 KiB
C
157 lines
3.9 KiB
C
/* $Id: cf-enabler.c,v 1.4 2004/02/22 22:44:36 kkojima Exp $
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*
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* linux/drivers/block/cf-enabler.c
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2000 Toshiharu Nozawa
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* Copyright (C) 2001 A&D Co., Ltd.
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*
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* Enable the CF configuration.
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*/
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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/*
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* You can connect Compact Flash directly to the bus of SuperH.
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* This is the enabler for that.
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*
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* SIM: How generic is this really? It looks pretty board, or at
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* least SH sub-type, specific to me.
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* I know it doesn't work on the Overdrive!
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*/
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/*
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* 0xB8000000 : Attribute
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* 0xB8001000 : Common Memory
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* 0xBA000000 : I/O
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*/
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#if defined(CONFIG_IDE) && defined(CONFIG_CPU_SH4)
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/* SH4 can't access PCMCIA interface through P2 area.
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* we must remap it with appropreate attribute bit of the page set.
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* this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#if defined(CONFIG_CF_AREA6)
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#define slot_no 0
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#else
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#define slot_no 1
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#endif
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/* defined in mm/ioremap.c */
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extern void * p3_ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags);
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/* use this pointer to access to directly connected compact flash io area*/
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void *cf_io_base;
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static int __init allocate_cf_area(void)
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{
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pgprot_t prot;
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unsigned long paddrbase, psize;
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/* open I/O area window */
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paddrbase = virt_to_phys((void*)CONFIG_CF_BASE_ADDR);
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psize = PAGE_SIZE;
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prot = PAGE_KERNEL_PCC(slot_no, _PAGE_PCC_IO16);
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cf_io_base = p3_ioremap(paddrbase, psize, prot.pgprot);
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if (!cf_io_base) {
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printk("allocate_cf_area : can't open CF I/O window!\n");
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return -ENOMEM;
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}
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/* printk("p3_ioremap(paddr=0x%08lx, psize=0x%08lx, prot=0x%08lx)=0x%08lx\n",
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paddrbase, psize, prot.pgprot, cf_io_base);*/
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/* XXX : do we need attribute and common-memory area also? */
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return 0;
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}
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#endif
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static int __init cf_init_default(void)
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{
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/* You must have enabled the card, and set the level interrupt
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* before reaching this point. Possibly in boot ROM or boot loader.
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*/
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#if defined(CONFIG_IDE) && defined(CONFIG_CPU_SH4)
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allocate_cf_area();
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#endif
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#if defined(CONFIG_SH_UNKNOWN)
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/* This should be done in each board's init_xxx_irq. */
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make_imask_irq(14);
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disable_irq(14);
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#endif
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return 0;
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}
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#if defined(CONFIG_SH_SOLUTION_ENGINE)
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#include <asm/se/se.h>
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/*
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* SolutionEngine
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*
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* 0xB8400000 : Common Memory
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* 0xB8500000 : Attribute
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* 0xB8600000 : I/O
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*/
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static int __init cf_init_se(void)
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{
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if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
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return 0; /* Not detected */
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if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) {
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ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
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} else {
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ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
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}
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/*
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* PC-Card window open
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* flag == COMMON/ATTRIBUTE/IO
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*/
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/* common window open */
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ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */
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if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
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/* common mode & bus width 16bit SWAP = 1*/
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ctrl_outw(0x0b00, MRSHPC_MW0CR2);
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else
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/* common mode & bus width 16bit SWAP = 0*/
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ctrl_outw(0x0300, MRSHPC_MW0CR2);
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/* attribute window open */
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ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */
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if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
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/* attribute mode & bus width 16bit SWAP = 1*/
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ctrl_outw(0x0a00, MRSHPC_MW1CR2);
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else
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/* attribute mode & bus width 16bit SWAP = 0*/
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ctrl_outw(0x0200, MRSHPC_MW1CR2);
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/* I/O window open */
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ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */
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ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
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if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
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ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
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else
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ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
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ctrl_outw(0x2000, MRSHPC_ICR);
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ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
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ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
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return 0;
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}
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#endif
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int __init cf_init(void)
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{
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#if defined(CONFIG_SH_SOLUTION_ENGINE)
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if (MACH_SE)
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return cf_init_se();
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#endif
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return cf_init_default();
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}
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__initcall (cf_init);
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