3968cb49ab
Add framebuffer support for the AMD Geode LX graphics engine. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
199 lines
5.5 KiB
C
199 lines
5.5 KiB
C
#ifndef _LXFB_H_
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#define _LXFB_H_
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#include <linux/fb.h>
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#define OUTPUT_CRT 0x01
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#define OUTPUT_PANEL 0x02
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struct lxfb_par {
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int output;
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int panel_width;
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int panel_height;
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void __iomem *gp_regs;
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void __iomem *dc_regs;
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void __iomem *df_regs;
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};
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static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
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{
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return (((xres * (bpp >> 3)) + 7) & ~7);
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}
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void lx_set_mode(struct fb_info *);
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void lx_get_gamma(struct fb_info *, unsigned int *, int);
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void lx_set_gamma(struct fb_info *, unsigned int *, int);
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unsigned int lx_framebuffer_size(void);
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int lx_blank_display(struct fb_info *, int);
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void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
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unsigned int, unsigned int);
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/* MSRS */
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#define MSR_LX_GLD_CONFIG 0x48002001
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#define MSR_LX_GLCP_DOTPLL 0x4c000015
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#define MSR_LX_DF_PADSEL 0x48000011
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#define MSR_LX_DC_SPARE 0x80000011
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#define MSR_LX_DF_GLCONFIG 0x48002001
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#define MSR_LX_GLIU0_P2D_RO0 0x10000029
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#define GLCP_DOTPLL_RESET (1 << 0)
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#define GLCP_DOTPLL_BYPASS (1 << 15)
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#define GLCP_DOTPLL_HALFPIX (1 << 24)
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#define GLCP_DOTPLL_LOCK (1 << 25)
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#define DF_CONFIG_OUTPUT_MASK 0x38
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#define DF_OUTPUT_PANEL 0x08
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#define DF_OUTPUT_CRT 0x00
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#define DF_SIMULTANEOUS_CRT_AND_FP (1 << 15)
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#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF
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#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
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#define DC_SPARE_DISABLE_CFIFO_HGO 0x00000800
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#define DC_SPARE_VFIFO_ARB_SELECT 0x00000400
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#define DC_SPARE_WM_LPEN_OVRD 0x00000200
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#define DC_SPARE_LOAD_WM_LPEN_MASK 0x00000100
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#define DC_SPARE_DISABLE_INIT_VID_PRI 0x00000080
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#define DC_SPARE_DISABLE_VFIFO_WM 0x00000040
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#define DC_SPARE_DISABLE_CWD_CHECK 0x00000020
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#define DC_SPARE_PIX8_PAN_FIX 0x00000010
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#define DC_SPARE_FIRST_REQ_MASK 0x00000002
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/* Registers */
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#define DC_UNLOCK 0x00
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#define DC_UNLOCK_CODE 0x4758
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#define DC_GENERAL_CFG 0x04
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#define DC_GCFG_DFLE (1 << 0)
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#define DC_GCFG_VIDE (1 << 3)
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#define DC_GCFG_VGAE (1 << 7)
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#define DC_GCFG_CMPE (1 << 5)
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#define DC_GCFG_DECE (1 << 6)
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#define DC_GCFG_FDTY (1 << 17)
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#define DC_DISPLAY_CFG 0x08
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#define DC_DCFG_TGEN (1 << 0)
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#define DC_DCFG_GDEN (1 << 3)
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#define DC_DCFG_VDEN (1 << 4)
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#define DC_DCFG_TRUP (1 << 6)
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#define DC_DCFG_DCEN (1 << 24)
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#define DC_DCFG_PALB (1 << 25)
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#define DC_DCFG_VISL (1 << 27)
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#define DC_DCFG_16BPP 0x0
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#define DC_DCFG_DISP_MODE_MASK 0x00000300
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#define DC_DCFG_DISP_MODE_8BPP 0x00000000
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#define DC_DCFG_DISP_MODE_16BPP 0x00000100
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#define DC_DCFG_DISP_MODE_24BPP 0x00000200
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#define DC_DCFG_DISP_MODE_32BPP 0x00000300
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#define DC_ARB_CFG 0x0C
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#define DC_FB_START 0x10
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#define DC_CB_START 0x14
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#define DC_CURSOR_START 0x18
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#define DC_DV_TOP 0x2C
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#define DC_DV_TOP_ENABLE (1 << 0)
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#define DC_LINE_SIZE 0x30
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#define DC_GRAPHICS_PITCH 0x34
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#define DC_H_ACTIVE_TIMING 0x40
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#define DC_H_BLANK_TIMING 0x44
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#define DC_H_SYNC_TIMING 0x48
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#define DC_V_ACTIVE_TIMING 0x50
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#define DC_V_BLANK_TIMING 0x54
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#define DC_V_SYNC_TIMING 0x58
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#define DC_FB_ACTIVE 0x5C
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#define DC_PAL_ADDRESS 0x70
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#define DC_PAL_DATA 0x74
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#define DC_PHY_MEM_OFFSET 0x84
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#define DC_DV_CTL 0x88
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#define DC_DV_LINE_SIZE_MASK 0x00000C00
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#define DC_DV_LINE_SIZE_1024 0x00000000
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#define DC_DV_LINE_SIZE_2048 0x00000400
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#define DC_DV_LINE_SIZE_4096 0x00000800
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#define DC_DV_LINE_SIZE_8192 0x00000C00
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#define DC_GFX_SCALE 0x90
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#define DC_IRQ_FILT_CTL 0x94
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#define DC_IRQ 0xC8
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#define DC_IRQ_MASK (1 << 0)
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#define DC_VSYNC_IRQ_MASK (1 << 1)
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#define DC_IRQ_STATUS (1 << 20)
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#define DC_VSYNC_IRQ_STATUS (1 << 21)
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#define DC_GENLCK_CTRL 0xD4
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#define DC_GENLCK_ENABLE (1 << 18)
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#define DC_GC_ALPHA_FLICK_ENABLE (1 << 25)
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#define DC_GC_FLICKER_FILTER_ENABLE (1 << 24)
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#define DC_GC_FLICKER_FILTER_MASK (0x0F << 28)
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#define DC_COLOR_KEY 0xB8
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#define DC_CLR_KEY_ENABLE (1 << 24)
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#define DC3_DV_LINE_SIZE_MASK 0x00000C00
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#define DC3_DV_LINE_SIZE_1024 0x00000000
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#define DC3_DV_LINE_SIZE_2048 0x00000400
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#define DC3_DV_LINE_SIZE_4096 0x00000800
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#define DC3_DV_LINE_SIZE_8192 0x00000C00
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#define DF_VIDEO_CFG 0x0
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#define DF_VCFG_VID_EN (1 << 0)
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#define DF_DISPLAY_CFG 0x08
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#define DF_DCFG_CRT_EN (1 << 0)
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#define DF_DCFG_HSYNC_EN (1 << 1)
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#define DF_DCFG_VSYNC_EN (1 << 2)
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#define DF_DCFG_DAC_BL_EN (1 << 3)
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#define DF_DCFG_CRT_HSYNC_POL (1 << 8)
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#define DF_DCFG_CRT_VSYNC_POL (1 << 9)
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#define DF_DCFG_GV_PAL_BYP (1 << 21)
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#define DF_DCFG_CRT_SYNC_SKW_INIT 0x10000
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#define DF_DCFG_CRT_SYNC_SKW_MASK 0x1c000
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#define DF_DCFG_PWR_SEQ_DLY_INIT 0x80000
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#define DF_DCFG_PWR_SEQ_DLY_MASK 0xe0000
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#define DF_MISC 0x50
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#define DF_MISC_GAM_BYPASS (1 << 0)
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#define DF_MISC_DAC_PWRDN (1 << 10)
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#define DF_MISC_A_PWRDN (1 << 11)
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#define DF_PAR 0x38
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#define DF_PDR 0x40
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#define DF_ALPHA_CONTROL_1 0xD8
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#define DF_VIDEO_REQUEST 0x120
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#define DF_PANEL_TIM1 0x400
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#define DF_DEFAULT_TFT_PMTIM1 0x0
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#define DF_PANEL_TIM2 0x408
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#define DF_DEFAULT_TFT_PMTIM2 0x08000000
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#define DF_FP_PM 0x410
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#define DF_FP_PM_P (1 << 24)
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#define DF_DITHER_CONTROL 0x418
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#define DF_DEFAULT_TFT_DITHCTL 0x00000070
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#define GP_BLT_STATUS 0x44
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#define GP_BS_BLT_BUSY (1 << 0)
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#define GP_BS_CB_EMPTY (1 << 4)
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#endif
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