fa7a7883fe
Add support for the DMA blocks in the S3C64XX series of CPUS, which are based on the ARM PL080 PrimeCell system. Unfortunately, these DMA controllers diverge from the PL080 design by adding another DMA controller register and configuration for OneNAND. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
73 lines
1.4 KiB
C
73 lines
1.4 KiB
C
/* linux/arch/arm/mach-s3c6400/include/mach/dma.h
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C6400 - DMA support
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*/
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#ifndef __ASM_ARCH_DMA_H
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#define __ASM_ARCH_DMA_H __FILE__
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#define S3C_DMA_CHANNELS (16)
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/* see mach-s3c2410/dma.h for notes on dma channel numbers */
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/* Note, for the S3C64XX architecture we keep the DMACH_
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* defines in the order they are allocated to [S]DMA0/[S]DMA1
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* so that is easy to do DHACH_ -> DMA controller conversion
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*/
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enum dma_ch {
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/* DMA0/SDMA0 */
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DMACH_UART0 = 0,
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DMACH_UART0_SRC2,
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DMACH_UART1,
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DMACH_UART1_SRC2,
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DMACH_UART2,
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DMACH_UART2_SRC2,
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DMACH_UART3,
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DMACH_UART3_SRC2,
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DMACH_PCM0_TX,
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DMACH_PCM0_RX,
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DMACH_I2S0_OUT,
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DMACH_I2S0_IN,
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DMACH_SPI0_TX,
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DMACH_SPI0_RX,
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DMACH_HSI_I2SV40_TX,
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DMACH_HSI_I2SV40_RX,
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/* DMA1/SDMA1 */
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DMACH_PCM1_TX = 16,
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DMACH_PCM1_RX,
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DMACH_I2S1_OUT,
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DMACH_I2S1_IN,
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DMACH_SPI1_TX,
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DMACH_SPI1_RX,
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DMACH_AC97_PCMOUT,
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DMACH_AC97_PCMIN,
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DMACH_AC97_MICIN,
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DMACH_PWM,
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DMACH_IRDA,
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DMACH_EXTERNAL,
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DMACH_RES1,
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DMACH_RES2,
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DMACH_SECURITY_RX, /* SDMA1 only */
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DMACH_SECURITY_TX, /* SDMA1 only */
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DMACH_MAX /* the end */
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};
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static __inline__ int s3c_dma_has_circular(void)
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{
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/* we will be supporting ciruclar buffers as soon as we have DMA
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* engine support.
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*/
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return 1;
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}
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#define S3C2410_DMAF_CIRCULAR (1 << 0)
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#include <plat/dma.h>
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#endif /* __ASM_ARCH_IRQ_H */
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