a4f500381a
kvm_minstate.h : Marcos about Min save routines. lapic.h: apic structure definition. vcpu.h : routions related to vcpu virtualization. vti.h : Some macros or routines for VT support on Itanium. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
290 lines
7.6 KiB
C
290 lines
7.6 KiB
C
/*
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* vti.h: prototype for generial vt related interface
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* Copyright (c) 2004, Intel Corporation.
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*
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* Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
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* Fred Yang (fred.yang@intel.com)
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* Kun Tian (Kevin Tian) (kevin.tian@intel.com)
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*
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* Copyright (c) 2007, Intel Corporation.
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* Zhang xiantao <xiantao.zhang@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*/
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#ifndef _KVM_VT_I_H
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#define _KVM_VT_I_H
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#ifndef __ASSEMBLY__
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#include <asm/page.h>
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#include <linux/kvm_host.h>
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/* define itr.i and itr.d in ia64_itr function */
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#define ITR 0x01
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#define DTR 0x02
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#define IaDTR 0x03
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#define IA64_TR_VMM 6 /*itr6, dtr6 : maps vmm code, vmbuffer*/
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#define IA64_TR_VM_DATA 7 /*dtr7 : maps current vm data*/
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#define RR6 (6UL<<61)
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#define RR7 (7UL<<61)
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/* config_options in pal_vp_init_env */
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#define VP_INITIALIZE 1UL
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#define VP_FR_PMC 1UL<<1
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#define VP_OPCODE 1UL<<8
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#define VP_CAUSE 1UL<<9
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#define VP_FW_ACC 1UL<<63
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/* init vp env with initializing vm_buffer */
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#define VP_INIT_ENV_INITALIZE (VP_INITIALIZE | VP_FR_PMC |\
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VP_OPCODE | VP_CAUSE | VP_FW_ACC)
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/* init vp env without initializing vm_buffer */
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#define VP_INIT_ENV VP_FR_PMC | VP_OPCODE | VP_CAUSE | VP_FW_ACC
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#define PAL_VP_CREATE 265
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/* Stacked Virt. Initializes a new VPD for the operation of
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* a new virtual processor in the virtual environment.
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*/
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#define PAL_VP_ENV_INFO 266
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/*Stacked Virt. Returns the parameters needed to enter a virtual environment.*/
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#define PAL_VP_EXIT_ENV 267
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/*Stacked Virt. Allows a logical processor to exit a virtual environment.*/
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#define PAL_VP_INIT_ENV 268
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/*Stacked Virt. Allows a logical processor to enter a virtual environment.*/
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#define PAL_VP_REGISTER 269
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/*Stacked Virt. Register a different host IVT for the virtual processor.*/
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#define PAL_VP_RESUME 270
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/* Renamed from PAL_VP_RESUME */
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#define PAL_VP_RESTORE 270
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/*Stacked Virt. Resumes virtual processor operation on the logical processor.*/
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#define PAL_VP_SUSPEND 271
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/* Renamed from PAL_VP_SUSPEND */
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#define PAL_VP_SAVE 271
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/* Stacked Virt. Suspends operation for the specified virtual processor on
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* the logical processor.
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*/
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#define PAL_VP_TERMINATE 272
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/* Stacked Virt. Terminates operation for the specified virtual processor.*/
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union vac {
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unsigned long value;
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struct {
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int a_int:1;
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int a_from_int_cr:1;
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int a_to_int_cr:1;
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int a_from_psr:1;
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int a_from_cpuid:1;
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int a_cover:1;
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int a_bsw:1;
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long reserved:57;
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};
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};
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union vdc {
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unsigned long value;
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struct {
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int d_vmsw:1;
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int d_extint:1;
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int d_ibr_dbr:1;
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int d_pmc:1;
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int d_to_pmd:1;
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int d_itm:1;
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long reserved:58;
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};
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};
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struct vpd {
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union vac vac;
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union vdc vdc;
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unsigned long virt_env_vaddr;
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unsigned long reserved1[29];
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unsigned long vhpi;
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unsigned long reserved2[95];
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unsigned long vgr[16];
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unsigned long vbgr[16];
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unsigned long vnat;
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unsigned long vbnat;
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unsigned long vcpuid[5];
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unsigned long reserved3[11];
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unsigned long vpsr;
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unsigned long vpr;
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unsigned long reserved4[76];
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union {
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unsigned long vcr[128];
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struct {
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unsigned long dcr;
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unsigned long itm;
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unsigned long iva;
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unsigned long rsv1[5];
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unsigned long pta;
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unsigned long rsv2[7];
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unsigned long ipsr;
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unsigned long isr;
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unsigned long rsv3;
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unsigned long iip;
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unsigned long ifa;
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unsigned long itir;
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unsigned long iipa;
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unsigned long ifs;
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unsigned long iim;
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unsigned long iha;
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unsigned long rsv4[38];
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unsigned long lid;
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unsigned long ivr;
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unsigned long tpr;
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unsigned long eoi;
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unsigned long irr[4];
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unsigned long itv;
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unsigned long pmv;
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unsigned long cmcv;
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unsigned long rsv5[5];
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unsigned long lrr0;
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unsigned long lrr1;
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unsigned long rsv6[46];
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};
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};
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unsigned long reserved5[128];
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unsigned long reserved6[3456];
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unsigned long vmm_avail[128];
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unsigned long reserved7[4096];
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};
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#define PAL_PROC_VM_BIT (1UL << 40)
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#define PAL_PROC_VMSW_BIT (1UL << 54)
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static inline s64 ia64_pal_vp_env_info(u64 *buffer_size,
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u64 *vp_env_info)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_ENV_INFO, 0, 0, 0);
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*buffer_size = iprv.v0;
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*vp_env_info = iprv.v1;
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_exit_env(u64 iva)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_EXIT_ENV, (u64)iva, 0, 0);
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_init_env(u64 config_options, u64 pbase_addr,
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u64 vbase_addr, u64 *vsa_base)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_INIT_ENV, config_options, pbase_addr,
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vbase_addr);
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*vsa_base = iprv.v0;
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_restore(u64 *vpd, u64 pal_proc_vector)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_RESTORE, (u64)vpd, pal_proc_vector, 0);
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return iprv.status;
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}
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static inline s64 ia64_pal_vp_save(u64 *vpd, u64 pal_proc_vector)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL_STK(iprv, PAL_VP_SAVE, (u64)vpd, pal_proc_vector, 0);
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return iprv.status;
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}
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#endif
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/*VPD field offset*/
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#define VPD_VAC_START_OFFSET 0
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#define VPD_VDC_START_OFFSET 8
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#define VPD_VHPI_START_OFFSET 256
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#define VPD_VGR_START_OFFSET 1024
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#define VPD_VBGR_START_OFFSET 1152
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#define VPD_VNAT_START_OFFSET 1280
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#define VPD_VBNAT_START_OFFSET 1288
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#define VPD_VCPUID_START_OFFSET 1296
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#define VPD_VPSR_START_OFFSET 1424
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#define VPD_VPR_START_OFFSET 1432
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#define VPD_VRSE_CFLE_START_OFFSET 1440
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#define VPD_VCR_START_OFFSET 2048
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#define VPD_VTPR_START_OFFSET 2576
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#define VPD_VRR_START_OFFSET 3072
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#define VPD_VMM_VAIL_START_OFFSET 31744
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/*Virtualization faults*/
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#define EVENT_MOV_TO_AR 1
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#define EVENT_MOV_TO_AR_IMM 2
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#define EVENT_MOV_FROM_AR 3
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#define EVENT_MOV_TO_CR 4
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#define EVENT_MOV_FROM_CR 5
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#define EVENT_MOV_TO_PSR 6
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#define EVENT_MOV_FROM_PSR 7
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#define EVENT_ITC_D 8
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#define EVENT_ITC_I 9
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#define EVENT_MOV_TO_RR 10
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#define EVENT_MOV_TO_DBR 11
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#define EVENT_MOV_TO_IBR 12
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#define EVENT_MOV_TO_PKR 13
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#define EVENT_MOV_TO_PMC 14
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#define EVENT_MOV_TO_PMD 15
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#define EVENT_ITR_D 16
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#define EVENT_ITR_I 17
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#define EVENT_MOV_FROM_RR 18
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#define EVENT_MOV_FROM_DBR 19
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#define EVENT_MOV_FROM_IBR 20
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#define EVENT_MOV_FROM_PKR 21
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#define EVENT_MOV_FROM_PMC 22
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#define EVENT_MOV_FROM_CPUID 23
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#define EVENT_SSM 24
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#define EVENT_RSM 25
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#define EVENT_PTC_L 26
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#define EVENT_PTC_G 27
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#define EVENT_PTC_GA 28
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#define EVENT_PTR_D 29
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#define EVENT_PTR_I 30
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#define EVENT_THASH 31
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#define EVENT_TTAG 32
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#define EVENT_TPA 33
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#define EVENT_TAK 34
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#define EVENT_PTC_E 35
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#define EVENT_COVER 36
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#define EVENT_RFI 37
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#define EVENT_BSW_0 38
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#define EVENT_BSW_1 39
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#define EVENT_VMSW 40
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/**PAL virtual services offsets */
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#define PAL_VPS_RESUME_NORMAL 0x0000
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#define PAL_VPS_RESUME_HANDLER 0x0400
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#define PAL_VPS_SYNC_READ 0x0800
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#define PAL_VPS_SYNC_WRITE 0x0c00
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#define PAL_VPS_SET_PENDING_INTERRUPT 0x1000
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#define PAL_VPS_THASH 0x1400
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#define PAL_VPS_TTAG 0x1800
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#define PAL_VPS_RESTORE 0x1c00
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#define PAL_VPS_SAVE 0x2000
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#endif/* _VT_I_H*/
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