fbc9be106e
This patch moves OMAP4 soc specific code from 4430sdp board file. The change is necessary so that newer board support can be added with minimal changes. This will be also problematic for multi-board, multi-omap builds. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
176 lines
4 KiB
C
176 lines
4 KiB
C
/*
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* OMAP4 SMP source file. It contains platform specific fucntions
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* needed for the linux smp kernel.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Platform file needed for the OMAP4 SMP. This file is based on arm
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* realview smp platform.
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* * Copyright (c) 2002 ARM Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/localtimer.h>
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#include <asm/smp_scu.h>
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#include <mach/hardware.h>
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#include <mach/omap4-common.h>
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/* SCU base address */
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static void __iomem *scu_base;
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/*
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* Use SCU config register to count number of cores
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*/
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static inline unsigned int get_core_count(void)
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{
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if (scu_base)
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return scu_get_core_count(scu_base);
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return 1;
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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trace_hardirqs_off();
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/*
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* If any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_cpu_init(0, gic_cpu_base_addr);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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* omap_secondary_startup() routine will hold the secondary core till
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* the AuxCoreBoot1 register is updated with cpu state
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* A barrier is added to ensure that write buffer is drained
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*/
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omap_modify_auxcoreboot0(0x200, 0x0);
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flush_cache_all();
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smp_wmb();
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/*
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return 0;
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}
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static void __init wakeup_secondary(void)
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{
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/*
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* Write the address of secondary startup routine into the
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* AuxCoreBoot1 where ROM code will jump and start executing
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* on secondary core once out of WFE
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* A barrier is added to ensure that write buffer is drained
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*/
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omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
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smp_wmb();
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/*
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* Send a 'sev' to wake the secondary core from WFE.
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* Drain the outstanding writes to memory
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*/
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dsb();
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set_event();
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mb();
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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void __init smp_init_cpus(void)
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{
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unsigned int i, ncores;
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/* Never released */
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scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
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BUG_ON(!scu_base);
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ncores = get_core_count();
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned int ncores = get_core_count();
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unsigned int cpu = smp_processor_id();
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int i;
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/* sanity check */
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if (ncores == 0) {
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printk(KERN_ERR
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"OMAP4: strange core count of 0? Default to 1\n");
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ncores = 1;
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}
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if (ncores > NR_CPUS) {
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printk(KERN_WARNING
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"OMAP4: no. of cores (%d) greater than configured "
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"maximum of %d - clipping\n",
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ncores, NR_CPUS);
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ncores = NR_CPUS;
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}
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smp_store_cpu_info(cpu);
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/*
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* are we trying to boot more cores than exist?
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*/
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if (max_cpus > ncores)
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max_cpus = ncores;
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/*
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* Initialise the present map, which describes the set of CPUs
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* actually populated at the present time.
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*/
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for (i = 0; i < max_cpus; i++)
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set_cpu_present(i, true);
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if (max_cpus > 1) {
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/*
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* Enable the local timer or broadcast device for the
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* boot CPU, but only if we have more than one CPU.
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*/
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percpu_timer_setup();
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/*
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* Initialise the SCU and wake up the secondary core using
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* wakeup_secondary().
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*/
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scu_enable(scu_base);
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wakeup_secondary();
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}
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}
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