148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
/*
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* arch/arm/mach-ep93xx/clock.c
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* Clock control for Cirrus EP93xx chips.
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <asm/div64.h>
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#include <mach/hardware.h>
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struct clk {
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unsigned long rate;
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int users;
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u32 enable_reg;
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u32 enable_mask;
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};
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static struct clk clk_uart = {
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.rate = 14745600,
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};
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static struct clk clk_pll1;
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static struct clk clk_f;
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static struct clk clk_h;
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static struct clk clk_p;
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static struct clk clk_pll2;
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static struct clk clk_usb_host = {
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.enable_reg = EP93XX_SYSCON_CLOCK_CONTROL,
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.enable_mask = EP93XX_SYSCON_CLOCK_USH_EN,
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};
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#define INIT_CK(dev,con,ck) \
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{ .dev_id = dev, .con_id = con, .clk = ck }
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static struct clk_lookup clocks[] = {
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INIT_CK("apb:uart1", NULL, &clk_uart),
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INIT_CK("apb:uart2", NULL, &clk_uart),
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INIT_CK("apb:uart3", NULL, &clk_uart),
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INIT_CK(NULL, "pll1", &clk_pll1),
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INIT_CK(NULL, "fclk", &clk_f),
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INIT_CK(NULL, "hclk", &clk_h),
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INIT_CK(NULL, "pclk", &clk_p),
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INIT_CK(NULL, "pll2", &clk_pll2),
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INIT_CK(NULL, "usb_host", &clk_usb_host),
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};
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int clk_enable(struct clk *clk)
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{
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if (!clk->users++ && clk->enable_reg) {
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u32 value;
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value = __raw_readl(clk->enable_reg);
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__raw_writel(value | clk->enable_mask, clk->enable_reg);
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}
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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if (!--clk->users && clk->enable_reg) {
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u32 value;
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value = __raw_readl(clk->enable_reg);
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__raw_writel(value & ~clk->enable_mask, clk->enable_reg);
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}
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
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static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
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static char pclk_divisors[] = { 1, 2, 4, 8 };
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/*
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* PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
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*/
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static unsigned long calc_pll_rate(u32 config_word)
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{
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unsigned long long rate;
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int i;
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rate = 14745600;
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rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
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rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
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do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
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for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
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rate >>= 1;
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return (unsigned long)rate;
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}
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static int __init ep93xx_clock_init(void)
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{
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u32 value;
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int i;
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value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
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if (!(value & 0x00800000)) { /* PLL1 bypassed? */
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clk_pll1.rate = 14745600;
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} else {
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clk_pll1.rate = calc_pll_rate(value);
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}
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clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
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clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
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clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
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value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
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if (!(value & 0x00080000)) { /* PLL2 bypassed? */
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clk_pll2.rate = 14745600;
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} else if (value & 0x00040000) { /* PLL2 enabled? */
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clk_pll2.rate = calc_pll_rate(value);
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} else {
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clk_pll2.rate = 0;
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}
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clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
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printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
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clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
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printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
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clk_f.rate / 1000000, clk_h.rate / 1000000,
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clk_p.rate / 1000000);
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for (i = 0; i < ARRAY_SIZE(clocks); i++)
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clkdev_add(&clocks[i]);
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return 0;
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}
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arch_initcall(ep93xx_clock_init);
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