3538a2cf0e
The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
26 lines
597 B
C
26 lines
597 B
C
/*
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* This header provides constants for Samsung audio subsystem
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* clock controller.
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*
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* The constants defined in this header are being used in dts
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* and exynos audss driver.
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*/
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#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
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#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
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#define EXYNOS_MOUT_AUDSS 0
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#define EXYNOS_MOUT_I2S 1
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#define EXYNOS_DOUT_SRP 2
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#define EXYNOS_DOUT_AUD_BUS 3
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#define EXYNOS_DOUT_I2S 4
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#define EXYNOS_SRP_CLK 5
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#define EXYNOS_I2S_BUS 6
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#define EXYNOS_SCLK_I2S 7
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#define EXYNOS_PCM_BUS 8
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#define EXYNOS_SCLK_PCM 9
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#define EXYNOS_ADMA 10
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#define EXYNOS_AUDSS_MAX_CLKS 11
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#endif
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