7e83f2ad3e
The original memory map for the sbc8548 had the 64MB SODIMM flash
device misaligned by 8MB to allow a window of address space for
the soldered on 8MB device -- i.e.
start end CS<n> width Desc.
----------------------------------------------------------
fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB)
ff80_0000 ffff_ffff CS0 8 Boot flash (8MB)
However, if we want to change the configuration so that it boots
off the 64MB flash, it is in turn then aligned with a 64MB boundary,
starting at fc00_0000 (and the 8MB @ fb80_0000 -> fbff_ffff).
This makes for complicated updates, since what is the beginning
of the physical device is 8MB into its address space in the default
configuration shown above.
This issue was fixed as of u-boot commit 3fd673cf363bc86ed42eff713d4
("sbc8548: relocate 64MB user flash to sane boundary") -- in which
the SODIMM was mapped to ec00_0000 (natively aligned under efff_ffff)
and so when JP12/SW2.8 are switched, it will be a a simple 0xec --> 0xfc
mapping between the two instances.
Here we make the associated changes in the localbus flash memory
map in the dts file: indicating the 64MB device starts at ec00_0000
and that the tail end of the 64MB device (last 2 sectors) can contain
a bootloader image.
The partitions for both flash devices get a clean-up; there were
non-meaningful assignments in there that probably originated from
the MPC8548CDS on which the file was based on. Now there is just
the categorization of free space and bootloader images.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
110 lines
2.4 KiB
Text
110 lines
2.4 KiB
Text
/*
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* SBC8548 Device Tree Source
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*
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* Copyright 2007 Wind River Systems Inc.
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*
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* Paul Gortmaker (see MAINTAINERS for contact information)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/include/ "sbc8548-pre.dtsi"
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/{
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localbus@e0000000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0xe0000000 0x5000>;
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interrupt-parent = <&mpic>;
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ranges = <0x0 0x0 0xff800000 0x00800000 /*8MB Flash*/
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0x3 0x0 0xf0000000 0x04000000 /*64MB SDRAM*/
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0x4 0x0 0xf4000000 0x04000000 /*64MB SDRAM*/
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0x5 0x0 0xf8000000 0x00b10000 /* EPLD */
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0x6 0x0 0xec000000 0x04000000>; /*64MB Flash*/
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,JS28F640", "cfi-flash";
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reg = <0x0 0x0 0x800000>;
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bank-width = <1>;
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device-width = <1>;
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partition@0x0 {
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label = "space";
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/* FF800000 -> FFF9FFFF */
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reg = <0x00000000 0x007a0000>;
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};
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partition@0x7a0000 {
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label = "bootloader";
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/* FFFA0000 -> FFFFFFFF */
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reg = <0x007a0000 0x00060000>;
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read-only;
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};
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};
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epld@5,0 {
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compatible = "wrs,epld-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x5 0x0 0x00b10000>;
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ranges = <
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0x0 0x0 0x5 0x000000 0x1fff /* LED */
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0x1 0x0 0x5 0x100000 0x1fff /* Switches */
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0x3 0x0 0x5 0x300000 0x1fff /* HW Rev. */
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0xb 0x0 0x5 0xb00000 0x1fff /* EEPROM */
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>;
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led@0,0 {
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compatible = "led";
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reg = <0x0 0x0 0x1fff>;
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};
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switches@1,0 {
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compatible = "switches";
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reg = <0x1 0x0 0x1fff>;
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};
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hw-rev@3,0 {
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compatible = "hw-rev";
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reg = <0x3 0x0 0x1fff>;
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};
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eeprom@b,0 {
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compatible = "eeprom";
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reg = <0xb 0 0x1fff>;
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};
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};
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alt-flash@6,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x6 0x0 0x04000000>;
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compatible = "intel,JS28F128", "cfi-flash";
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bank-width = <4>;
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device-width = <1>;
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partition@0x0 {
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label = "space";
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/* EC000000 -> EFEFFFFF */
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reg = <0x00000000 0x03f00000>;
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};
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partition@0x03f00000 {
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label = "bootloader";
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/* EFF00000 -> EFFFFFFF */
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reg = <0x03f00000 0x00100000>;
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read-only;
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};
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};
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};
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};
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/include/ "sbc8548-post.dtsi"
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