323 lines
7.8 KiB
C
323 lines
7.8 KiB
C
/*
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* Mailbox reservation modules for OMAP2
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*
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* Copyright (C) 2006 Nokia Corporation
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* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
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* and Paul Mundt <paul.mundt@nokia.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/mailbox.h>
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#include <mach/irqs.h>
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#define MAILBOX_REVISION 0x00
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#define MAILBOX_SYSCONFIG 0x10
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#define MAILBOX_SYSSTATUS 0x14
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#define MAILBOX_MESSAGE_0 0x40
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#define MAILBOX_MESSAGE_1 0x44
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#define MAILBOX_MESSAGE_2 0x48
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#define MAILBOX_MESSAGE_3 0x4c
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#define MAILBOX_MESSAGE_4 0x50
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#define MAILBOX_MESSAGE_5 0x54
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#define MAILBOX_FIFOSTATUS_0 0x80
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#define MAILBOX_FIFOSTATUS_1 0x84
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#define MAILBOX_FIFOSTATUS_2 0x88
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#define MAILBOX_FIFOSTATUS_3 0x8c
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#define MAILBOX_FIFOSTATUS_4 0x90
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#define MAILBOX_FIFOSTATUS_5 0x94
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#define MAILBOX_MSGSTATUS_0 0xc0
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#define MAILBOX_MSGSTATUS_1 0xc4
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#define MAILBOX_MSGSTATUS_2 0xc8
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#define MAILBOX_MSGSTATUS_3 0xcc
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#define MAILBOX_MSGSTATUS_4 0xd0
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#define MAILBOX_MSGSTATUS_5 0xd4
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#define MAILBOX_IRQSTATUS_0 0x100
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#define MAILBOX_IRQENABLE_0 0x104
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#define MAILBOX_IRQSTATUS_1 0x108
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#define MAILBOX_IRQENABLE_1 0x10c
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#define MAILBOX_IRQSTATUS_2 0x110
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#define MAILBOX_IRQENABLE_2 0x114
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#define MAILBOX_IRQSTATUS_3 0x118
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#define MAILBOX_IRQENABLE_3 0x11c
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static unsigned long mbox_base;
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#define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
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#define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
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struct omap_mbox2_fifo {
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unsigned long msg;
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unsigned long fifo_stat;
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unsigned long msg_stat;
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};
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struct omap_mbox2_priv {
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struct omap_mbox2_fifo tx_fifo;
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struct omap_mbox2_fifo rx_fifo;
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unsigned long irqenable;
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unsigned long irqstatus;
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u32 newmsg_bit;
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u32 notfull_bit;
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};
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static struct clk *mbox_ick_handle;
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq);
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static inline unsigned int mbox_read_reg(unsigned int reg)
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{
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return __raw_readl(mbox_base + reg);
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}
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static inline void mbox_write_reg(unsigned int val, unsigned int reg)
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{
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__raw_writel(val, mbox_base + reg);
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}
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/* Mailbox H/W preparations */
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static int omap2_mbox_startup(struct omap_mbox *mbox)
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{
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unsigned int l;
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mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
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if (IS_ERR(mbox_ick_handle)) {
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printk("Could not get mailboxes_ick\n");
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return -ENODEV;
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}
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clk_enable(mbox_ick_handle);
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/* set smart-idle & autoidle */
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l = mbox_read_reg(MAILBOX_SYSCONFIG);
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l |= 0x00000011;
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mbox_write_reg(l, MAILBOX_SYSCONFIG);
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omap2_mbox_enable_irq(mbox, IRQ_RX);
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return 0;
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}
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static void omap2_mbox_shutdown(struct omap_mbox *mbox)
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{
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clk_disable(mbox_ick_handle);
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clk_put(mbox_ick_handle);
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}
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/* Mailbox FIFO handle functions */
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static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_msg_t) mbox_read_reg(fifo->msg);
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}
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static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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mbox_write_reg(msg, fifo->msg);
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}
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static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
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return (mbox_read_reg(fifo->msg_stat) == 0);
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}
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static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
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{
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struct omap_mbox2_fifo *fifo =
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&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
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return (mbox_read_reg(fifo->fifo_stat));
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}
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/* Mailbox IRQ handle functions */
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static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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l = mbox_read_reg(p->irqenable);
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l |= bit;
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mbox_write_reg(l, p->irqenable);
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}
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static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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l = mbox_read_reg(p->irqenable);
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l &= ~bit;
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mbox_write_reg(l, p->irqenable);
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}
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static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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mbox_write_reg(bit, p->irqstatus);
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}
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static int omap2_mbox_is_irq(struct omap_mbox *mbox,
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omap_mbox_type_t irq)
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{
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struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
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u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
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u32 enable = mbox_read_reg(p->irqenable);
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u32 status = mbox_read_reg(p->irqstatus);
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return (enable & status & bit);
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}
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static struct omap_mbox_ops omap2_mbox_ops = {
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.type = OMAP_MBOX_TYPE2,
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.startup = omap2_mbox_startup,
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.shutdown = omap2_mbox_shutdown,
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.fifo_read = omap2_mbox_fifo_read,
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.fifo_write = omap2_mbox_fifo_write,
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.fifo_empty = omap2_mbox_fifo_empty,
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.fifo_full = omap2_mbox_fifo_full,
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.enable_irq = omap2_mbox_enable_irq,
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.disable_irq = omap2_mbox_disable_irq,
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.ack_irq = omap2_mbox_ack_irq,
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.is_irq = omap2_mbox_is_irq,
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};
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/*
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* MAILBOX 0: ARM -> DSP,
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* MAILBOX 1: ARM <- DSP.
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* MAILBOX 2: ARM -> IVA,
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* MAILBOX 3: ARM <- IVA.
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*/
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/* FIXME: the following structs should be filled automatically by the user id */
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/* DSP */
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static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE_0,
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.fifo_stat = MAILBOX_FIFOSTATUS_0,
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE_1,
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.msg_stat = MAILBOX_MSGSTATUS_1,
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},
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.irqenable = MAILBOX_IRQENABLE_0,
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.irqstatus = MAILBOX_IRQSTATUS_0,
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.notfull_bit = MAILBOX_IRQ_NOTFULL(0),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
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};
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struct omap_mbox mbox_dsp_info = {
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.name = "dsp",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_dsp_priv,
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};
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EXPORT_SYMBOL(mbox_dsp_info);
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/* IVA */
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static struct omap_mbox2_priv omap2_mbox_iva_priv = {
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.tx_fifo = {
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.msg = MAILBOX_MESSAGE_2,
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.fifo_stat = MAILBOX_FIFOSTATUS_2,
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},
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.rx_fifo = {
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.msg = MAILBOX_MESSAGE_3,
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.msg_stat = MAILBOX_MSGSTATUS_3,
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},
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.irqenable = MAILBOX_IRQENABLE_3,
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.irqstatus = MAILBOX_IRQSTATUS_3,
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.notfull_bit = MAILBOX_IRQ_NOTFULL(2),
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.newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
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};
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static struct omap_mbox mbox_iva_info = {
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.name = "iva",
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.ops = &omap2_mbox_ops,
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.priv = &omap2_mbox_iva_priv,
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};
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static int __init omap2_mbox_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret = 0;
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if (pdev->num_resources != 3) {
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dev_err(&pdev->dev, "invalid number of resources: %d\n",
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pdev->num_resources);
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return -ENODEV;
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}
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/* MBOX base */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (unlikely(!res)) {
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dev_err(&pdev->dev, "invalid mem resource\n");
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return -ENODEV;
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}
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mbox_base = res->start;
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/* DSP IRQ */
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (unlikely(!res)) {
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dev_err(&pdev->dev, "invalid irq resource\n");
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return -ENODEV;
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}
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mbox_dsp_info.irq = res->start;
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ret = omap_mbox_register(&mbox_dsp_info);
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/* IVA IRQ */
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
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if (unlikely(!res)) {
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dev_err(&pdev->dev, "invalid irq resource\n");
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return -ENODEV;
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}
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mbox_iva_info.irq = res->start;
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ret = omap_mbox_register(&mbox_iva_info);
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return ret;
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}
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static int omap2_mbox_remove(struct platform_device *pdev)
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{
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omap_mbox_unregister(&mbox_dsp_info);
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return 0;
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}
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static struct platform_driver omap2_mbox_driver = {
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.probe = omap2_mbox_probe,
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.remove = omap2_mbox_remove,
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.driver = {
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.name = "mailbox",
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},
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};
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static int __init omap2_mbox_init(void)
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{
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return platform_driver_register(&omap2_mbox_driver);
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}
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static void __exit omap2_mbox_exit(void)
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{
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platform_driver_unregister(&omap2_mbox_driver);
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}
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module_init(omap2_mbox_init);
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module_exit(omap2_mbox_exit);
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MODULE_LICENSE("GPL");
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