Jiancheng Xue 6c9da387c8 clk: hisilicon: add CRG driver for hi3519 soc ... The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2016-05-06 11:13:32 -07:00
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clk-hi3519.c	clk: hisilicon: add CRG driver for hi3519 soc	2016-05-06 11:13:32 -07:00
clk-hi3620.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hi6220-stub.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hi6220.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hip04.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk-hix5hd2.c	clk: hisilicon: Remove CLK_IS_ROOT	2016-03-02 17:43:32 -08:00
clk.c	clk: hisilicon: export some hisilicon APIs to modules	2016-05-06 11:13:31 -07:00
clk.h	clk: hisilicon: export some hisilicon APIs to modules	2016-05-06 11:13:31 -07:00
clkdivider-hi6220.c
clkgate-separated.c
Kconfig	clk: hisilicon: add CRG driver for hi3519 soc	2016-05-06 11:13:32 -07:00
Makefile	clk: hisilicon: add CRG driver for hi3519 soc	2016-05-06 11:13:32 -07:00
reset.c	reset: hisilicon: add reset controller driver for hisilicon SOCs	2016-05-06 11:13:29 -07:00
reset.h	reset: hisilicon: add reset controller driver for hisilicon SOCs	2016-05-06 11:13:29 -07:00