17ae4b40b4
We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Cc: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
379 lines
12 KiB
C
379 lines
12 KiB
C
/*
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* Author: Daniel Thompson <daniel.thompson@linaro.org>
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*
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* Inspired by clk-asm9260.c .
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#define STM32F4_RCC_PLLCFGR 0x04
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#define STM32F4_RCC_CFGR 0x08
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#define STM32F4_RCC_AHB1ENR 0x30
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#define STM32F4_RCC_AHB2ENR 0x34
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#define STM32F4_RCC_AHB3ENR 0x38
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#define STM32F4_RCC_APB1ENR 0x40
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#define STM32F4_RCC_APB2ENR 0x44
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struct stm32f4_gate_data {
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u8 offset;
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u8 bit_idx;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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};
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static const struct stm32f4_gate_data stm32f4_gates[] __initconst = {
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{ STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
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{ STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
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{ STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
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{ STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
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{ STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
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CLK_IGNORE_UNUSED },
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{ STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
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{ STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
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{ STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
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{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
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{ STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
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{ STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
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{ STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" },
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};
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/*
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* MAX_CLKS is the maximum value in the enumeration below plus the combined
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* hweight of stm32f42xx_gate_map (plus one).
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*/
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#define MAX_CLKS 74
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enum { SYSTICK, FCLK };
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/*
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* This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
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* have gate bits associated with them. Its combined hweight is 71.
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*/
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static const u64 stm32f42xx_gate_map[] = { 0x000000f17ef417ffull,
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0x0000000000000001ull,
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0x04777f33f6fec9ffull };
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static struct clk *clks[MAX_CLKS];
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static DEFINE_SPINLOCK(stm32f4_clk_lock);
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static void __iomem *base;
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/*
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* "Multiplier" device for APBx clocks.
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*
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* The APBx dividers are power-of-two dividers and, if *not* running in 1:1
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* mode, they also tap out the one of the low order state bits to run the
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* timers. ST datasheets represent this feature as a (conditional) clock
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* multiplier.
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*/
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struct clk_apb_mul {
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struct clk_hw hw;
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u8 bit_idx;
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};
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#define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
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static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_apb_mul *am = to_clk_apb_mul(hw);
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if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
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return parent_rate * 2;
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return parent_rate;
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}
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static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_apb_mul *am = to_clk_apb_mul(hw);
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unsigned long mult = 1;
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if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
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mult = 2;
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
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unsigned long best_parent = rate / mult;
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*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
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}
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return *prate * mult;
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}
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static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* We must report success but we can do so unconditionally because
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* clk_apb_mul_round_rate returns values that ensure this call is a
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* nop.
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*/
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return 0;
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}
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static const struct clk_ops clk_apb_mul_factor_ops = {
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.round_rate = clk_apb_mul_round_rate,
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.set_rate = clk_apb_mul_set_rate,
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.recalc_rate = clk_apb_mul_recalc_rate,
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};
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static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags, u8 bit_idx)
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{
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struct clk_apb_mul *am;
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struct clk_init_data init;
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struct clk *clk;
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am = kzalloc(sizeof(*am), GFP_KERNEL);
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if (!am)
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return ERR_PTR(-ENOMEM);
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am->bit_idx = bit_idx;
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am->hw.init = &init;
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init.name = name;
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init.ops = &clk_apb_mul_factor_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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clk = clk_register(dev, &am->hw);
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if (IS_ERR(clk))
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kfree(am);
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return clk;
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}
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/*
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* Decode current PLL state and (statically) model the state we inherit from
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* the bootloader.
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*/
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static void stm32f4_rcc_register_pll(const char *hse_clk, const char *hsi_clk)
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{
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unsigned long pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
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unsigned long pllm = pllcfgr & 0x3f;
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unsigned long plln = (pllcfgr >> 6) & 0x1ff;
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unsigned long pllp = BIT(((pllcfgr >> 16) & 3) + 1);
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const char *pllsrc = pllcfgr & BIT(22) ? hse_clk : hsi_clk;
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unsigned long pllq = (pllcfgr >> 24) & 0xf;
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clk_register_fixed_factor(NULL, "vco", pllsrc, 0, plln, pllm);
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clk_register_fixed_factor(NULL, "pll", "vco", 0, 1, pllp);
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clk_register_fixed_factor(NULL, "pll48", "vco", 0, 1, pllq);
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}
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/*
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* Converts the primary and secondary indices (as they appear in DT) to an
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* offset into our struct clock array.
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*/
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static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
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{
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u64 table[ARRAY_SIZE(stm32f42xx_gate_map)];
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if (primary == 1) {
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if (WARN_ON(secondary > FCLK))
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return -EINVAL;
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return secondary;
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}
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memcpy(table, stm32f42xx_gate_map, sizeof(table));
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/* only bits set in table can be used as indices */
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if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
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0 == (table[BIT_ULL_WORD(secondary)] &
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BIT_ULL_MASK(secondary))))
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return -EINVAL;
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/* mask out bits above our current index */
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table[BIT_ULL_WORD(secondary)] &=
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GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
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return FCLK + hweight64(table[0]) +
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(BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
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(BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
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}
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static struct clk *
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stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
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{
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int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
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if (i < 0)
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return ERR_PTR(-EINVAL);
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return clks[i];
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}
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static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
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static const struct clk_div_table ahb_div_table[] = {
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{ 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
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{ 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
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{ 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
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{ 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
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{ 0 },
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};
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static const struct clk_div_table apb_div_table[] = {
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{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
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{ 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
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{ 0 },
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};
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static void __init stm32f4_rcc_init(struct device_node *np)
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{
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const char *hse_clk;
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int n;
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("%s: unable to map resource", np->name);
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return;
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}
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hse_clk = of_clk_get_parent_name(np, 0);
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clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
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16000000, 160000);
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stm32f4_rcc_register_pll(hse_clk, "hsi");
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sys_parents[1] = hse_clk;
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clk_register_mux_table(
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NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
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base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
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clk_register_divider_table(NULL, "ahb_div", "sys",
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CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
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4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
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clk_register_divider_table(NULL, "apb1_div", "ahb_div",
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CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
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10, 3, 0, apb_div_table, &stm32f4_clk_lock);
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clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
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CLK_SET_RATE_PARENT, 12);
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clk_register_divider_table(NULL, "apb2_div", "ahb_div",
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CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
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13, 3, 0, apb_div_table, &stm32f4_clk_lock);
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clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
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CLK_SET_RATE_PARENT, 15);
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clks[SYSTICK] = clk_register_fixed_factor(NULL, "systick", "ahb_div",
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0, 1, 8);
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clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div",
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0, 1, 1);
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for (n = 0; n < ARRAY_SIZE(stm32f4_gates); n++) {
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const struct stm32f4_gate_data *gd = &stm32f4_gates[n];
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unsigned int secondary =
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8 * (gd->offset - STM32F4_RCC_AHB1ENR) + gd->bit_idx;
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int idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
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if (idx < 0)
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goto fail;
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clks[idx] = clk_register_gate(
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NULL, gd->name, gd->parent_name, gd->flags,
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base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
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if (IS_ERR(clks[n])) {
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pr_err("%s: Unable to register leaf clock %s\n",
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np->full_name, gd->name);
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goto fail;
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}
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}
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of_clk_add_provider(np, stm32f4_rcc_lookup_clk, NULL);
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return;
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fail:
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iounmap(base);
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}
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CLK_OF_DECLARE(stm32f4_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
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