3542a113ab
The SH DMA driver wrongly assigns negative cookies to transfer descriptors, also, its chaining of partial descriptors is broken. The latter problem is usually invisible, because maximum transfer size per chunk is 16M, but if you artificially set this limit lower, the driver fails. Since cookies are also used in chunk management, both these problems are fixed in one patch. As side effects a possible memory leak, when descriptors are prepared, but not submitted, and multiple races have also been fixed. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
67 lines
1.9 KiB
C
67 lines
1.9 KiB
C
/*
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* Renesas SuperH DMA Engine support
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*
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __DMA_SHDMA_H
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#define __DMA_SHDMA_H
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
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struct sh_dmae_regs {
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u32 sar; /* SAR / source address */
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u32 dar; /* DAR / destination address */
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u32 tcr; /* TCR / transfer count */
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};
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struct sh_desc {
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struct sh_dmae_regs hw;
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struct list_head node;
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struct dma_async_tx_descriptor async_tx;
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dma_cookie_t cookie;
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int chunks;
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int mark;
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};
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struct device;
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struct sh_dmae_chan {
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dma_cookie_t completed_cookie; /* The maximum cookie completed */
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spinlock_t desc_lock; /* Descriptor operation lock */
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struct list_head ld_queue; /* Link descriptors queue */
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struct list_head ld_free; /* Link descriptors free */
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struct dma_chan common; /* DMA common channel */
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struct device *dev; /* Channel device */
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struct tasklet_struct tasklet; /* Tasklet */
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int descs_allocated; /* desc count */
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int id; /* Raw id of this channel */
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char dev_id[16]; /* unique name per DMAC of channel */
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/* Set chcr */
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int (*set_chcr)(struct sh_dmae_chan *sh_chan, u32 regs);
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/* Set DMA resource */
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int (*set_dmars)(struct sh_dmae_chan *sh_chan, u16 res);
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};
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struct sh_dmae_device {
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struct dma_device common;
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struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
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struct sh_dmae_pdata pdata;
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};
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#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
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#define to_sh_desc(lh) container_of(lh, struct sh_desc, node)
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#define tx_to_sh_desc(tx) container_of(tx, struct sh_desc, async_tx)
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#endif /* __DMA_SHDMA_H */
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