16ee792e45
* 'next/devel' of git://git.linaro.org/people/arnd/arm-soc: (50 commits) ARM: tegra: update defconfig arm/tegra: Harmony: Configure PMC for low-level interrupts arm/tegra: device tree support for ventana board arm/tegra: add support for ventana pinmuxing arm/tegra: prepare Seaboard pinmux code for derived boards arm/tegra: pinmux: ioremap registers gpio/tegra: Convert to a platform device arm/tegra: Convert pinmux driver to a platform device arm/dt: Tegra: Add pinmux node to tegra20.dtsi arm/tegra: Prep boards for gpio/pinmux conversion to pdevs ARM: mx5: fix clock usage for suspend ARM i.MX entry-macro.S: remove now unused code ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLER ARM i.MX tzic: add handle_irq function ARM i.MX avic: add handle_irq function ARM: mx25: Add the missing IIM base definition ARM i.MX avic: convert to use generic irq chip mx31moboard: Add poweroff support ARM: mach-qong: Add watchdog support ARM: davinci: AM18x: Add wl1271/wlan support ... Fix up conflicts in: arch/arm/mach-at91/at91sam9g45.c arch/arm/mach-mx5/devices-imx53.h arch/arm/plat-mxc/include/mach/memory.h
706 lines
15 KiB
C
706 lines
15 KiB
C
/*
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* Copyright (C) 2010,2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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* Erik Gilling <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/resource.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/fsl_devices.h>
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#include <linux/serial_8250.h>
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#include <linux/i2c-tegra.h>
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#include <linux/platform_data/tegra_usb.h>
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#include <asm/pmu.h>
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#include <mach/irqs.h>
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#include <mach/iomap.h>
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#include <mach/dma.h>
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#include <mach/usb_phy.h>
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#include "gpio-names.h"
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#include "devices.h"
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static struct resource gpio_resource[] = {
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[0] = {
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.start = TEGRA_GPIO_BASE,
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.end = TEGRA_GPIO_BASE + TEGRA_GPIO_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = INT_GPIO1,
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.end = INT_GPIO1,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = INT_GPIO2,
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.end = INT_GPIO2,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = INT_GPIO3,
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.end = INT_GPIO3,
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.flags = IORESOURCE_IRQ,
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},
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[4] = {
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.start = INT_GPIO4,
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.end = INT_GPIO4,
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.flags = IORESOURCE_IRQ,
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},
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[5] = {
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.start = INT_GPIO5,
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.end = INT_GPIO5,
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.flags = IORESOURCE_IRQ,
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},
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[6] = {
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.start = INT_GPIO6,
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.end = INT_GPIO6,
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.flags = IORESOURCE_IRQ,
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},
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[7] = {
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.start = INT_GPIO7,
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.end = INT_GPIO7,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device tegra_gpio_device = {
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.name = "tegra-gpio",
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.id = -1,
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.resource = gpio_resource,
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.num_resources = ARRAY_SIZE(gpio_resource),
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};
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static struct resource pinmux_resource[] = {
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[0] = {
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/* Tri-state registers */
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.start = TEGRA_APB_MISC_BASE + 0x14,
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.end = TEGRA_APB_MISC_BASE + 0x20 + 3,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* Mux registers */
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.start = TEGRA_APB_MISC_BASE + 0x80,
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.end = TEGRA_APB_MISC_BASE + 0x9c + 3,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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/* Pull-up/down registers */
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.start = TEGRA_APB_MISC_BASE + 0xa0,
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.end = TEGRA_APB_MISC_BASE + 0xb0 + 3,
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.flags = IORESOURCE_MEM,
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},
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[3] = {
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/* Pad control registers */
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.start = TEGRA_APB_MISC_BASE + 0x868,
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.end = TEGRA_APB_MISC_BASE + 0x90c + 3,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device tegra_pinmux_device = {
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.name = "tegra-pinmux",
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.id = -1,
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.resource = pinmux_resource,
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.num_resources = ARRAY_SIZE(pinmux_resource),
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};
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static struct resource i2c_resource1[] = {
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[0] = {
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.start = INT_I2C,
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.end = INT_I2C,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_I2C_BASE,
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.end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource i2c_resource2[] = {
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[0] = {
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.start = INT_I2C2,
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.end = INT_I2C2,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_I2C2_BASE,
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.end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource i2c_resource3[] = {
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[0] = {
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.start = INT_I2C3,
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.end = INT_I2C3,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_I2C3_BASE,
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.end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource i2c_resource4[] = {
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[0] = {
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.start = INT_DVC,
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.end = INT_DVC,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_DVC_BASE,
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.end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
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.bus_clk_rate = 400000,
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};
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static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
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.bus_clk_rate = 400000,
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};
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static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
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.bus_clk_rate = 400000,
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};
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static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
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.bus_clk_rate = 400000,
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};
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struct platform_device tegra_i2c_device1 = {
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.name = "tegra-i2c",
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.id = 0,
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.resource = i2c_resource1,
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.num_resources = ARRAY_SIZE(i2c_resource1),
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.dev = {
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.platform_data = &tegra_i2c1_platform_data,
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},
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};
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struct platform_device tegra_i2c_device2 = {
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.name = "tegra-i2c",
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.id = 1,
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.resource = i2c_resource2,
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.num_resources = ARRAY_SIZE(i2c_resource2),
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.dev = {
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.platform_data = &tegra_i2c2_platform_data,
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},
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};
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struct platform_device tegra_i2c_device3 = {
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.name = "tegra-i2c",
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.id = 2,
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.resource = i2c_resource3,
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.num_resources = ARRAY_SIZE(i2c_resource3),
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.dev = {
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.platform_data = &tegra_i2c3_platform_data,
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},
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};
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struct platform_device tegra_i2c_device4 = {
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.name = "tegra-i2c",
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.id = 3,
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.resource = i2c_resource4,
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.num_resources = ARRAY_SIZE(i2c_resource4),
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.dev = {
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.platform_data = &tegra_dvc_platform_data,
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},
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};
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static struct resource spi_resource1[] = {
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[0] = {
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.start = INT_S_LINK1,
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.end = INT_S_LINK1,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SPI1_BASE,
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.end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource spi_resource2[] = {
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[0] = {
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.start = INT_SPI_2,
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.end = INT_SPI_2,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SPI2_BASE,
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.end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource spi_resource3[] = {
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[0] = {
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.start = INT_SPI_3,
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.end = INT_SPI_3,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SPI3_BASE,
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.end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource spi_resource4[] = {
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[0] = {
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.start = INT_SPI_4,
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.end = INT_SPI_4,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SPI4_BASE,
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.end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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struct platform_device tegra_spi_device1 = {
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.name = "spi_tegra",
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.id = 0,
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.resource = spi_resource1,
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.num_resources = ARRAY_SIZE(spi_resource1),
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct platform_device tegra_spi_device2 = {
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.name = "spi_tegra",
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.id = 1,
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.resource = spi_resource2,
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.num_resources = ARRAY_SIZE(spi_resource2),
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct platform_device tegra_spi_device3 = {
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.name = "spi_tegra",
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.id = 2,
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.resource = spi_resource3,
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.num_resources = ARRAY_SIZE(spi_resource3),
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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struct platform_device tegra_spi_device4 = {
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.name = "spi_tegra",
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.id = 3,
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.resource = spi_resource4,
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.num_resources = ARRAY_SIZE(spi_resource4),
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.dev = {
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.coherent_dma_mask = 0xffffffff,
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},
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};
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static struct resource sdhci_resource1[] = {
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[0] = {
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.start = INT_SDMMC1,
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.end = INT_SDMMC1,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SDMMC1_BASE,
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.end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource sdhci_resource2[] = {
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[0] = {
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.start = INT_SDMMC2,
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.end = INT_SDMMC2,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SDMMC2_BASE,
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.end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource sdhci_resource3[] = {
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[0] = {
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.start = INT_SDMMC3,
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.end = INT_SDMMC3,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SDMMC3_BASE,
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.end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource sdhci_resource4[] = {
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[0] = {
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.start = INT_SDMMC4,
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.end = INT_SDMMC4,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = TEGRA_SDMMC4_BASE,
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.end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
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.flags = IORESOURCE_MEM,
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},
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};
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/* board files should fill in platform_data register the devices themselvs.
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* See board-harmony.c for an example
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*/
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struct platform_device tegra_sdhci_device1 = {
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.name = "sdhci-tegra",
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.id = 0,
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.resource = sdhci_resource1,
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.num_resources = ARRAY_SIZE(sdhci_resource1),
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};
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struct platform_device tegra_sdhci_device2 = {
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.name = "sdhci-tegra",
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.id = 1,
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.resource = sdhci_resource2,
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.num_resources = ARRAY_SIZE(sdhci_resource2),
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};
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struct platform_device tegra_sdhci_device3 = {
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.name = "sdhci-tegra",
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.id = 2,
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.resource = sdhci_resource3,
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.num_resources = ARRAY_SIZE(sdhci_resource3),
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};
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struct platform_device tegra_sdhci_device4 = {
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.name = "sdhci-tegra",
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.id = 3,
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.resource = sdhci_resource4,
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.num_resources = ARRAY_SIZE(sdhci_resource4),
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};
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static struct resource tegra_usb1_resources[] = {
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[0] = {
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.start = TEGRA_USB_BASE,
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.end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = INT_USB,
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.end = INT_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource tegra_usb2_resources[] = {
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[0] = {
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.start = TEGRA_USB2_BASE,
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.end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = INT_USB2,
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.end = INT_USB2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource tegra_usb3_resources[] = {
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[0] = {
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.start = TEGRA_USB3_BASE,
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.end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = INT_USB3,
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.end = INT_USB3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
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/* All existing boards use GPIO PV0 for phy reset */
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.reset_gpio = TEGRA_GPIO_PV0,
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.clk = "cdev2",
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};
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static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
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.operating_mode = TEGRA_USB_OTG,
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.power_down_on_bus_suspend = 1,
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};
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static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
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.phy_config = &tegra_ehci2_ulpi_phy_config,
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.operating_mode = TEGRA_USB_HOST,
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.power_down_on_bus_suspend = 1,
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};
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static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
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.operating_mode = TEGRA_USB_HOST,
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.power_down_on_bus_suspend = 1,
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};
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static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
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struct platform_device tegra_ehci1_device = {
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.name = "tegra-ehci",
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.id = 0,
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.dev = {
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.dma_mask = &tegra_ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &tegra_ehci1_pdata,
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},
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.resource = tegra_usb1_resources,
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.num_resources = ARRAY_SIZE(tegra_usb1_resources),
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};
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struct platform_device tegra_ehci2_device = {
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.name = "tegra-ehci",
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.id = 1,
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.dev = {
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.dma_mask = &tegra_ehci_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &tegra_ehci2_pdata,
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},
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.resource = tegra_usb2_resources,
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.num_resources = ARRAY_SIZE(tegra_usb2_resources),
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};
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struct platform_device tegra_ehci3_device = {
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.name = "tegra-ehci",
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.id = 2,
|
|
.dev = {
|
|
.dma_mask = &tegra_ehci_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &tegra_ehci3_pdata,
|
|
},
|
|
.resource = tegra_usb3_resources,
|
|
.num_resources = ARRAY_SIZE(tegra_usb3_resources),
|
|
};
|
|
|
|
static struct resource tegra_pmu_resources[] = {
|
|
[0] = {
|
|
.start = INT_CPU0_PMU_INTR,
|
|
.end = INT_CPU0_PMU_INTR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
[1] = {
|
|
.start = INT_CPU1_PMU_INTR,
|
|
.end = INT_CPU1_PMU_INTR,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_pmu_device = {
|
|
.name = "arm-pmu",
|
|
.id = ARM_PMU_DEVICE_CPU,
|
|
.num_resources = ARRAY_SIZE(tegra_pmu_resources),
|
|
.resource = tegra_pmu_resources,
|
|
};
|
|
|
|
static struct resource tegra_uarta_resources[] = {
|
|
[0] = {
|
|
.start = TEGRA_UARTA_BASE,
|
|
.end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = INT_UARTA,
|
|
.end = INT_UARTA,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct resource tegra_uartb_resources[] = {
|
|
[0] = {
|
|
.start = TEGRA_UARTB_BASE,
|
|
.end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = INT_UARTB,
|
|
.end = INT_UARTB,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct resource tegra_uartc_resources[] = {
|
|
[0] = {
|
|
.start = TEGRA_UARTC_BASE,
|
|
.end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = INT_UARTC,
|
|
.end = INT_UARTC,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct resource tegra_uartd_resources[] = {
|
|
[0] = {
|
|
.start = TEGRA_UARTD_BASE,
|
|
.end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = INT_UARTD,
|
|
.end = INT_UARTD,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct resource tegra_uarte_resources[] = {
|
|
[0] = {
|
|
.start = TEGRA_UARTE_BASE,
|
|
.end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = INT_UARTE,
|
|
.end = INT_UARTE,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_uarta_device = {
|
|
.name = "tegra_uart",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(tegra_uarta_resources),
|
|
.resource = tegra_uarta_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_uartb_device = {
|
|
.name = "tegra_uart",
|
|
.id = 1,
|
|
.num_resources = ARRAY_SIZE(tegra_uartb_resources),
|
|
.resource = tegra_uartb_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_uartc_device = {
|
|
.name = "tegra_uart",
|
|
.id = 2,
|
|
.num_resources = ARRAY_SIZE(tegra_uartc_resources),
|
|
.resource = tegra_uartc_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_uartd_device = {
|
|
.name = "tegra_uart",
|
|
.id = 3,
|
|
.num_resources = ARRAY_SIZE(tegra_uartd_resources),
|
|
.resource = tegra_uartd_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_uarte_device = {
|
|
.name = "tegra_uart",
|
|
.id = 4,
|
|
.num_resources = ARRAY_SIZE(tegra_uarte_resources),
|
|
.resource = tegra_uarte_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
};
|
|
|
|
static struct resource i2s_resource1[] = {
|
|
[0] = {
|
|
.start = INT_I2S1,
|
|
.end = INT_I2S1,
|
|
.flags = IORESOURCE_IRQ
|
|
},
|
|
[1] = {
|
|
.start = TEGRA_DMA_REQ_SEL_I2S_1,
|
|
.end = TEGRA_DMA_REQ_SEL_I2S_1,
|
|
.flags = IORESOURCE_DMA
|
|
},
|
|
[2] = {
|
|
.start = TEGRA_I2S1_BASE,
|
|
.end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
|
|
.flags = IORESOURCE_MEM
|
|
}
|
|
};
|
|
|
|
static struct resource i2s_resource2[] = {
|
|
[0] = {
|
|
.start = INT_I2S2,
|
|
.end = INT_I2S2,
|
|
.flags = IORESOURCE_IRQ
|
|
},
|
|
[1] = {
|
|
.start = TEGRA_DMA_REQ_SEL_I2S2_1,
|
|
.end = TEGRA_DMA_REQ_SEL_I2S2_1,
|
|
.flags = IORESOURCE_DMA
|
|
},
|
|
[2] = {
|
|
.start = TEGRA_I2S2_BASE,
|
|
.end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
|
|
.flags = IORESOURCE_MEM
|
|
}
|
|
};
|
|
|
|
struct platform_device tegra_i2s_device1 = {
|
|
.name = "tegra-i2s",
|
|
.id = 0,
|
|
.resource = i2s_resource1,
|
|
.num_resources = ARRAY_SIZE(i2s_resource1),
|
|
};
|
|
|
|
struct platform_device tegra_i2s_device2 = {
|
|
.name = "tegra-i2s",
|
|
.id = 1,
|
|
.resource = i2s_resource2,
|
|
.num_resources = ARRAY_SIZE(i2s_resource2),
|
|
};
|
|
|
|
static struct resource tegra_das_resources[] = {
|
|
[0] = {
|
|
.start = TEGRA_APB_MISC_DAS_BASE,
|
|
.end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
struct platform_device tegra_das_device = {
|
|
.name = "tegra-das",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(tegra_das_resources),
|
|
.resource = tegra_das_resources,
|
|
};
|
|
|
|
struct platform_device tegra_pcm_device = {
|
|
.name = "tegra-pcm-audio",
|
|
.id = -1,
|
|
};
|