1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
912 lines
25 KiB
C
912 lines
25 KiB
C
/*
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* iSeries_pci.c
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*
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* Copyright (C) 2001 Allan Trautman, IBM Corporation
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*
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* iSeries specific routines for PCI.
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*
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* Based on code from pci.c and iSeries_pci.c 32bit
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/ide.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppcdebug.h>
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#include <asm/iommu.h>
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#include <asm/iSeries/HvCallPci.h>
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#include <asm/iSeries/HvCallSm.h>
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#include <asm/iSeries/HvCallXm.h>
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#include <asm/iSeries/LparData.h>
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#include <asm/iSeries/iSeries_irq.h>
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#include <asm/iSeries/iSeries_pci.h>
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#include <asm/iSeries/mf.h>
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#include "pci.h"
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extern unsigned long io_page_mask;
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/*
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* Forward declares of prototypes.
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*/
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static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn);
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static void scan_PHB_slots(struct pci_controller *Phb);
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static void scan_EADS_bridge(HvBusNumber Bus, HvSubBusNumber SubBus, int IdSel);
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static int scan_bridge_slot(HvBusNumber Bus, struct HvCallPci_BridgeInfo *Info);
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LIST_HEAD(iSeries_Global_Device_List);
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static int DeviceCount;
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/* Counters and control flags. */
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static long Pci_Io_Read_Count;
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static long Pci_Io_Write_Count;
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#if 0
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static long Pci_Cfg_Read_Count;
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static long Pci_Cfg_Write_Count;
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#endif
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static long Pci_Error_Count;
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static int Pci_Retry_Max = 3; /* Only retry 3 times */
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static int Pci_Error_Flag = 1; /* Set Retry Error on. */
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static struct pci_ops iSeries_pci_ops;
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/*
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* Table defines
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* Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
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*/
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#define IOMM_TABLE_MAX_ENTRIES 1024
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#define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
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#define BASE_IO_MEMORY 0xE000000000000000UL
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static unsigned long max_io_memory = 0xE000000000000000UL;
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static long current_iomm_table_entry;
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/*
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* Lookup Tables.
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*/
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static struct iSeries_Device_Node **iomm_table;
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static u8 *iobar_table;
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/*
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* Static and Global variables
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*/
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static char *pci_io_text = "iSeries PCI I/O";
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static DEFINE_SPINLOCK(iomm_table_lock);
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/*
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* iomm_table_initialize
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*
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* Allocates and initalizes the Address Translation Table and Bar
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* Tables to get them ready for use. Must be called before any
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* I/O space is handed out to the device BARs.
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*/
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static void iomm_table_initialize(void)
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{
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spin_lock(&iomm_table_lock);
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iomm_table = kmalloc(sizeof(*iomm_table) * IOMM_TABLE_MAX_ENTRIES,
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GFP_KERNEL);
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iobar_table = kmalloc(sizeof(*iobar_table) * IOMM_TABLE_MAX_ENTRIES,
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GFP_KERNEL);
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spin_unlock(&iomm_table_lock);
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if ((iomm_table == NULL) || (iobar_table == NULL))
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panic("PCI: I/O tables allocation failed.\n");
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}
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/*
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* iomm_table_allocate_entry
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*
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* Adds pci_dev entry in address translation table
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*
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* - Allocates the number of entries required in table base on BAR
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* size.
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* - Allocates starting at BASE_IO_MEMORY and increases.
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* - The size is round up to be a multiple of entry size.
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* - CurrentIndex is incremented to keep track of the last entry.
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* - Builds the resource entry for allocated BARs.
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*/
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static void iomm_table_allocate_entry(struct pci_dev *dev, int bar_num)
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{
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struct resource *bar_res = &dev->resource[bar_num];
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long bar_size = pci_resource_len(dev, bar_num);
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/*
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* No space to allocate, quick exit, skip Allocation.
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*/
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if (bar_size == 0)
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return;
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/*
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* Set Resource values.
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*/
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spin_lock(&iomm_table_lock);
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bar_res->name = pci_io_text;
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bar_res->start =
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IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry;
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bar_res->start += BASE_IO_MEMORY;
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bar_res->end = bar_res->start + bar_size - 1;
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/*
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* Allocate the number of table entries needed for BAR.
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*/
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while (bar_size > 0 ) {
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iomm_table[current_iomm_table_entry] = dev->sysdata;
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iobar_table[current_iomm_table_entry] = bar_num;
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bar_size -= IOMM_TABLE_ENTRY_SIZE;
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++current_iomm_table_entry;
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}
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max_io_memory = BASE_IO_MEMORY +
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(IOMM_TABLE_ENTRY_SIZE * current_iomm_table_entry);
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spin_unlock(&iomm_table_lock);
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}
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/*
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* allocate_device_bars
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*
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* - Allocates ALL pci_dev BAR's and updates the resources with the
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* BAR value. BARS with zero length will have the resources
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* The HvCallPci_getBarParms is used to get the size of the BAR
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* space. It calls iomm_table_allocate_entry to allocate
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* each entry.
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* - Loops through The Bar resources(0 - 5) including the ROM
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* is resource(6).
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*/
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static void allocate_device_bars(struct pci_dev *dev)
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{
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struct resource *bar_res;
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int bar_num;
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for (bar_num = 0; bar_num <= PCI_ROM_RESOURCE; ++bar_num) {
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bar_res = &dev->resource[bar_num];
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iomm_table_allocate_entry(dev, bar_num);
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}
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}
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/*
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* Log error information to system console.
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* Filter out the device not there errors.
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* PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
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* PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
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* PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
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*/
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static void pci_Log_Error(char *Error_Text, int Bus, int SubBus,
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int AgentId, int HvRc)
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{
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if (HvRc == 0x0302)
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return;
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printk(KERN_ERR "PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
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Error_Text, Bus, SubBus, AgentId, HvRc);
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}
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/*
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* build_device_node(u16 Bus, int SubBus, u8 DevFn)
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*/
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static struct iSeries_Device_Node *build_device_node(HvBusNumber Bus,
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HvSubBusNumber SubBus, int AgentId, int Function)
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{
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struct iSeries_Device_Node *node;
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PPCDBG(PPCDBG_BUSWALK,
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"-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
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Bus, SubBus, AgentId, Function);
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node = kmalloc(sizeof(struct iSeries_Device_Node), GFP_KERNEL);
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if (node == NULL)
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return NULL;
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memset(node, 0, sizeof(struct iSeries_Device_Node));
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list_add_tail(&node->Device_List, &iSeries_Global_Device_List);
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#if 0
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node->DsaAddr = ((u64)Bus << 48) + ((u64)SubBus << 40) + ((u64)0x10 << 32);
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#endif
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node->DsaAddr.DsaAddr = 0;
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node->DsaAddr.Dsa.busNumber = Bus;
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node->DsaAddr.Dsa.subBusNumber = SubBus;
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node->DsaAddr.Dsa.deviceId = 0x10;
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node->AgentId = AgentId;
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node->DevFn = PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId), Function);
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node->IoRetry = 0;
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iSeries_Get_Location_Code(node);
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return node;
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}
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/*
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* unsigned long __init find_and_init_phbs(void)
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*
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* Description:
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* This function checks for all possible system PCI host bridges that connect
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* PCI buses. The system hypervisor is queried as to the guest partition
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* ownership status. A pci_controller is built for any bus which is partially
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* owned or fully owned by this guest partition.
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*/
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unsigned long __init find_and_init_phbs(void)
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{
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struct pci_controller *phb;
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HvBusNumber bus;
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PPCDBG(PPCDBG_BUSWALK, "find_and_init_phbs Entry\n");
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/* Check all possible buses. */
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for (bus = 0; bus < 256; bus++) {
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int ret = HvCallXm_testBus(bus);
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if (ret == 0) {
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printk("bus %d appears to exist\n", bus);
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phb = (struct pci_controller *)kmalloc(sizeof(struct pci_controller), GFP_KERNEL);
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if (phb == NULL)
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return -ENOMEM;
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pci_setup_pci_controller(phb);
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phb->pci_mem_offset = phb->local_number = bus;
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phb->first_busno = bus;
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phb->last_busno = bus;
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phb->ops = &iSeries_pci_ops;
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PPCDBG(PPCDBG_BUSWALK, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
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phb, bus);
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/* Find and connect the devices. */
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scan_PHB_slots(phb);
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}
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/*
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* Check for Unexpected Return code, a clue that something
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* has gone wrong.
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*/
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else if (ret != 0x0301)
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printk(KERN_ERR "Unexpected Return on Probe(0x%04X): 0x%04X",
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bus, ret);
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}
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return 0;
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}
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/*
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* iSeries_pcibios_init
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*
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* Chance to initialize and structures or variable before PCI Bus walk.
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*/
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void iSeries_pcibios_init(void)
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{
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PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Entry.\n");
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iomm_table_initialize();
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find_and_init_phbs();
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io_page_mask = -1;
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PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_init Exit.\n");
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}
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/*
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* iSeries_pci_final_fixup(void)
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*/
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void __init iSeries_pci_final_fixup(void)
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{
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struct pci_dev *pdev = NULL;
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struct iSeries_Device_Node *node;
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char Buffer[256];
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int DeviceCount = 0;
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PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup Entry.\n");
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/* Fix up at the device node and pci_dev relationship */
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mf_display_src(0xC9000100);
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printk("pcibios_final_fixup\n");
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for_each_pci_dev(pdev) {
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node = find_Device_Node(pdev->bus->number, pdev->devfn);
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printk("pci dev %p (%x.%x), node %p\n", pdev,
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pdev->bus->number, pdev->devfn, node);
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if (node != NULL) {
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++DeviceCount;
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pdev->sysdata = (void *)node;
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node->PciDev = pdev;
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PPCDBG(PPCDBG_BUSWALK,
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"pdev 0x%p <==> DevNode 0x%p\n",
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pdev, node);
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allocate_device_bars(pdev);
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iSeries_Device_Information(pdev, Buffer,
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sizeof(Buffer));
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printk("%d. %s\n", DeviceCount, Buffer);
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iommu_devnode_init_iSeries(node);
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} else
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printk("PCI: Device Tree not found for 0x%016lX\n",
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(unsigned long)pdev);
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pdev->irq = node->Irq;
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}
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iSeries_activate_IRQs();
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mf_display_src(0xC9000200);
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}
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void pcibios_fixup_bus(struct pci_bus *PciBus)
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{
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PPCDBG(PPCDBG_BUSWALK, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
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PciBus->number);
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}
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void pcibios_fixup_resources(struct pci_dev *pdev)
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{
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PPCDBG(PPCDBG_BUSWALK, "fixup_resources pdev %p\n", pdev);
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}
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/*
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* Loop through each node function to find usable EADs bridges.
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*/
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static void scan_PHB_slots(struct pci_controller *Phb)
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{
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struct HvCallPci_DeviceInfo *DevInfo;
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HvBusNumber bus = Phb->local_number; /* System Bus */
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const HvSubBusNumber SubBus = 0; /* EADs is always 0. */
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int HvRc = 0;
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int IdSel;
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const int MaxAgents = 8;
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DevInfo = (struct HvCallPci_DeviceInfo*)
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kmalloc(sizeof(struct HvCallPci_DeviceInfo), GFP_KERNEL);
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if (DevInfo == NULL)
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return;
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/*
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* Probe for EADs Bridges
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*/
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for (IdSel = 1; IdSel < MaxAgents; ++IdSel) {
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HvRc = HvCallPci_getDeviceInfo(bus, SubBus, IdSel,
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ISERIES_HV_ADDR(DevInfo),
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sizeof(struct HvCallPci_DeviceInfo));
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if (HvRc == 0) {
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if (DevInfo->deviceType == HvCallPci_NodeDevice)
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scan_EADS_bridge(bus, SubBus, IdSel);
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else
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printk("PCI: Invalid System Configuration(0x%02X)"
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" for bus 0x%02x id 0x%02x.\n",
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DevInfo->deviceType, bus, IdSel);
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}
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else
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pci_Log_Error("getDeviceInfo", bus, SubBus, IdSel, HvRc);
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}
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kfree(DevInfo);
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}
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static void scan_EADS_bridge(HvBusNumber bus, HvSubBusNumber SubBus,
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int IdSel)
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{
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struct HvCallPci_BridgeInfo *BridgeInfo;
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HvAgentId AgentId;
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int Function;
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int HvRc;
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BridgeInfo = (struct HvCallPci_BridgeInfo *)
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kmalloc(sizeof(struct HvCallPci_BridgeInfo), GFP_KERNEL);
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if (BridgeInfo == NULL)
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return;
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/* Note: hvSubBus and irq is always be 0 at this level! */
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for (Function = 0; Function < 8; ++Function) {
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AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
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HvRc = HvCallXm_connectBusUnit(bus, SubBus, AgentId, 0);
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if (HvRc == 0) {
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printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
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bus, IdSel, Function, AgentId);
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/* Connect EADs: 0x18.00.12 = 0x00 */
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PPCDBG(PPCDBG_BUSWALK,
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"PCI:Connect EADs: 0x%02X.%02X.%02X\n",
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bus, SubBus, AgentId);
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HvRc = HvCallPci_getBusUnitInfo(bus, SubBus, AgentId,
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ISERIES_HV_ADDR(BridgeInfo),
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sizeof(struct HvCallPci_BridgeInfo));
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if (HvRc == 0) {
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printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
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BridgeInfo->busUnitInfo.deviceType,
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BridgeInfo->subBusNumber,
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BridgeInfo->maxAgents,
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BridgeInfo->maxSubBusNumber,
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BridgeInfo->logicalSlotNumber);
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PPCDBG(PPCDBG_BUSWALK,
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"PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
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BridgeInfo->busUnitInfo.deviceType,
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BridgeInfo->subBusNumber,
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BridgeInfo->maxAgents,
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BridgeInfo->maxSubBusNumber,
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BridgeInfo->logicalSlotNumber);
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if (BridgeInfo->busUnitInfo.deviceType ==
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HvCallPci_BridgeDevice) {
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/* Scan_Bridge_Slot...: 0x18.00.12 */
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scan_bridge_slot(bus, BridgeInfo);
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} else
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printk("PCI: Invalid Bridge Configuration(0x%02X)",
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BridgeInfo->busUnitInfo.deviceType);
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}
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} else if (HvRc != 0x000B)
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pci_Log_Error("EADs Connect",
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bus, SubBus, AgentId, HvRc);
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}
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kfree(BridgeInfo);
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}
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/*
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* This assumes that the node slot is always on the primary bus!
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*/
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static int scan_bridge_slot(HvBusNumber Bus,
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struct HvCallPci_BridgeInfo *BridgeInfo)
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{
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struct iSeries_Device_Node *node;
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HvSubBusNumber SubBus = BridgeInfo->subBusNumber;
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u16 VendorId = 0;
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int HvRc = 0;
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u8 Irq = 0;
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int IdSel = ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus);
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int Function = ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus);
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HvAgentId EADsIdSel = ISERIES_PCI_AGENTID(IdSel, Function);
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/* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
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Irq = iSeries_allocate_IRQ(Bus, 0, EADsIdSel);
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PPCDBG(PPCDBG_BUSWALK,
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"PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
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Bus, 0, EADsIdSel, Irq);
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/*
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* Connect all functions of any device found.
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*/
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for (IdSel = 1; IdSel <= BridgeInfo->maxAgents; ++IdSel) {
|
|
for (Function = 0; Function < 8; ++Function) {
|
|
HvAgentId AgentId = ISERIES_PCI_AGENTID(IdSel, Function);
|
|
HvRc = HvCallXm_connectBusUnit(Bus, SubBus,
|
|
AgentId, Irq);
|
|
if (HvRc != 0) {
|
|
pci_Log_Error("Connect Bus Unit",
|
|
Bus, SubBus, AgentId, HvRc);
|
|
continue;
|
|
}
|
|
|
|
HvRc = HvCallPci_configLoad16(Bus, SubBus, AgentId,
|
|
PCI_VENDOR_ID, &VendorId);
|
|
if (HvRc != 0) {
|
|
pci_Log_Error("Read Vendor",
|
|
Bus, SubBus, AgentId, HvRc);
|
|
continue;
|
|
}
|
|
printk("read vendor ID: %x\n", VendorId);
|
|
|
|
/* FoundDevice: 0x18.28.10 = 0x12AE */
|
|
PPCDBG(PPCDBG_BUSWALK,
|
|
"PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
|
|
Bus, SubBus, AgentId, VendorId, Irq);
|
|
HvRc = HvCallPci_configStore8(Bus, SubBus, AgentId,
|
|
PCI_INTERRUPT_LINE, Irq);
|
|
if (HvRc != 0)
|
|
pci_Log_Error("PciCfgStore Irq Failed!",
|
|
Bus, SubBus, AgentId, HvRc);
|
|
|
|
++DeviceCount;
|
|
node = build_device_node(Bus, SubBus, EADsIdSel, Function);
|
|
node->Vendor = VendorId;
|
|
node->Irq = Irq;
|
|
node->LogicalSlot = BridgeInfo->logicalSlotNumber;
|
|
|
|
} /* for (Function = 0; Function < 8; ++Function) */
|
|
} /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
|
|
return HvRc;
|
|
}
|
|
|
|
/*
|
|
* I/0 Memory copy MUST use mmio commands on iSeries
|
|
* To do; For performance, include the hv call directly
|
|
*/
|
|
void iSeries_memset_io(volatile void __iomem *dest, char c, size_t Count)
|
|
{
|
|
u8 ByteValue = c;
|
|
long NumberOfBytes = Count;
|
|
|
|
while (NumberOfBytes > 0) {
|
|
iSeries_Write_Byte(ByteValue, dest++);
|
|
-- NumberOfBytes;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(iSeries_memset_io);
|
|
|
|
void iSeries_memcpy_toio(volatile void __iomem *dest, void *source, size_t count)
|
|
{
|
|
char *src = source;
|
|
long NumberOfBytes = count;
|
|
|
|
while (NumberOfBytes > 0) {
|
|
iSeries_Write_Byte(*src++, dest++);
|
|
-- NumberOfBytes;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(iSeries_memcpy_toio);
|
|
|
|
void iSeries_memcpy_fromio(void *dest, const volatile void __iomem *src, size_t count)
|
|
{
|
|
char *dst = dest;
|
|
long NumberOfBytes = count;
|
|
|
|
while (NumberOfBytes > 0) {
|
|
*dst++ = iSeries_Read_Byte(src++);
|
|
-- NumberOfBytes;
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(iSeries_memcpy_fromio);
|
|
|
|
/*
|
|
* Look down the chain to find the matching Device Device
|
|
*/
|
|
static struct iSeries_Device_Node *find_Device_Node(int bus, int devfn)
|
|
{
|
|
struct list_head *pos;
|
|
|
|
list_for_each(pos, &iSeries_Global_Device_List) {
|
|
struct iSeries_Device_Node *node =
|
|
list_entry(pos, struct iSeries_Device_Node, Device_List);
|
|
|
|
if ((bus == ISERIES_BUS(node)) && (devfn == node->DevFn))
|
|
return node;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
#if 0
|
|
/*
|
|
* Returns the device node for the passed pci_dev
|
|
* Sanity Check Node PciDev to passed pci_dev
|
|
* If none is found, returns a NULL which the client must handle.
|
|
*/
|
|
static struct iSeries_Device_Node *get_Device_Node(struct pci_dev *pdev)
|
|
{
|
|
struct iSeries_Device_Node *node;
|
|
|
|
node = pdev->sysdata;
|
|
if (node == NULL || node->PciDev != pdev)
|
|
node = find_Device_Node(pdev->bus->number, pdev->devfn);
|
|
return node;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Config space read and write functions.
|
|
* For now at least, we look for the device node for the bus and devfn
|
|
* that we are asked to access. It may be possible to translate the devfn
|
|
* to a subbus and deviceid more directly.
|
|
*/
|
|
static u64 hv_cfg_read_func[4] = {
|
|
HvCallPciConfigLoad8, HvCallPciConfigLoad16,
|
|
HvCallPciConfigLoad32, HvCallPciConfigLoad32
|
|
};
|
|
|
|
static u64 hv_cfg_write_func[4] = {
|
|
HvCallPciConfigStore8, HvCallPciConfigStore16,
|
|
HvCallPciConfigStore32, HvCallPciConfigStore32
|
|
};
|
|
|
|
/*
|
|
* Read PCI config space
|
|
*/
|
|
static int iSeries_pci_read_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int size, u32 *val)
|
|
{
|
|
struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
|
|
u64 fn;
|
|
struct HvCallPci_LoadReturn ret;
|
|
|
|
if (node == NULL)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
if (offset > 255) {
|
|
*val = ~0;
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
}
|
|
|
|
fn = hv_cfg_read_func[(size - 1) & 3];
|
|
HvCall3Ret16(fn, &ret, node->DsaAddr.DsaAddr, offset, 0);
|
|
|
|
if (ret.rc != 0) {
|
|
*val = ~0;
|
|
return PCIBIOS_DEVICE_NOT_FOUND; /* or something */
|
|
}
|
|
|
|
*val = ret.value;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Write PCI config space
|
|
*/
|
|
|
|
static int iSeries_pci_write_config(struct pci_bus *bus, unsigned int devfn,
|
|
int offset, int size, u32 val)
|
|
{
|
|
struct iSeries_Device_Node *node = find_Device_Node(bus->number, devfn);
|
|
u64 fn;
|
|
u64 ret;
|
|
|
|
if (node == NULL)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
if (offset > 255)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
|
|
fn = hv_cfg_write_func[(size - 1) & 3];
|
|
ret = HvCall4(fn, node->DsaAddr.DsaAddr, offset, val, 0);
|
|
|
|
if (ret != 0)
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct pci_ops iSeries_pci_ops = {
|
|
.read = iSeries_pci_read_config,
|
|
.write = iSeries_pci_write_config
|
|
};
|
|
|
|
/*
|
|
* Check Return Code
|
|
* -> On Failure, print and log information.
|
|
* Increment Retry Count, if exceeds max, panic partition.
|
|
* -> If in retry, print and log success
|
|
*
|
|
* PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
|
|
* PCI: Device 23.90 ReadL Retry( 1)
|
|
* PCI: Device 23.90 ReadL Retry Successful(1)
|
|
*/
|
|
static int CheckReturnCode(char *TextHdr, struct iSeries_Device_Node *DevNode,
|
|
u64 ret)
|
|
{
|
|
if (ret != 0) {
|
|
++Pci_Error_Count;
|
|
++DevNode->IoRetry;
|
|
printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
|
|
TextHdr, DevNode->DsaAddr.Dsa.busNumber, DevNode->DevFn,
|
|
DevNode->IoRetry, (int)ret);
|
|
/*
|
|
* Bump the retry and check for retry count exceeded.
|
|
* If, Exceeded, panic the system.
|
|
*/
|
|
if ((DevNode->IoRetry > Pci_Retry_Max) &&
|
|
(Pci_Error_Flag > 0)) {
|
|
mf_display_src(0xB6000103);
|
|
panic_timeout = 0;
|
|
panic("PCI: Hardware I/O Error, SRC B6000103, "
|
|
"Automatic Reboot Disabled.\n");
|
|
}
|
|
return -1; /* Retry Try */
|
|
}
|
|
/* If retry was in progress, log success and rest retry count */
|
|
if (DevNode->IoRetry > 0)
|
|
DevNode->IoRetry = 0;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Translate the I/O Address into a device node, bar, and bar offset.
|
|
* Note: Make sure the passed variable end up on the stack to avoid
|
|
* the exposure of being device global.
|
|
*/
|
|
static inline struct iSeries_Device_Node *xlate_iomm_address(
|
|
const volatile void __iomem *IoAddress,
|
|
u64 *dsaptr, u64 *BarOffsetPtr)
|
|
{
|
|
unsigned long OrigIoAddr;
|
|
unsigned long BaseIoAddr;
|
|
unsigned long TableIndex;
|
|
struct iSeries_Device_Node *DevNode;
|
|
|
|
OrigIoAddr = (unsigned long __force)IoAddress;
|
|
if ((OrigIoAddr < BASE_IO_MEMORY) || (OrigIoAddr >= max_io_memory))
|
|
return NULL;
|
|
BaseIoAddr = OrigIoAddr - BASE_IO_MEMORY;
|
|
TableIndex = BaseIoAddr / IOMM_TABLE_ENTRY_SIZE;
|
|
DevNode = iomm_table[TableIndex];
|
|
|
|
if (DevNode != NULL) {
|
|
int barnum = iobar_table[TableIndex];
|
|
*dsaptr = DevNode->DsaAddr.DsaAddr | (barnum << 24);
|
|
*BarOffsetPtr = BaseIoAddr % IOMM_TABLE_ENTRY_SIZE;
|
|
} else
|
|
panic("PCI: Invalid PCI IoAddress detected!\n");
|
|
return DevNode;
|
|
}
|
|
|
|
/*
|
|
* Read MM I/O Instructions for the iSeries
|
|
* On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
|
|
* else, data is returned in big Endian format.
|
|
*
|
|
* iSeries_Read_Byte = Read Byte ( 8 bit)
|
|
* iSeries_Read_Word = Read Word (16 bit)
|
|
* iSeries_Read_Long = Read Long (32 bit)
|
|
*/
|
|
u8 iSeries_Read_Byte(const volatile void __iomem *IoAddress)
|
|
{
|
|
u64 BarOffset;
|
|
u64 dsa;
|
|
struct HvCallPci_LoadReturn ret;
|
|
struct iSeries_Device_Node *DevNode =
|
|
xlate_iomm_address(IoAddress, &dsa, &BarOffset);
|
|
|
|
if (DevNode == NULL) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if ((jiffies - last_jiffies) > 60 * HZ) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR "iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress);
|
|
return 0xff;
|
|
}
|
|
do {
|
|
++Pci_Io_Read_Count;
|
|
HvCall3Ret16(HvCallPciBarLoad8, &ret, dsa, BarOffset, 0);
|
|
} while (CheckReturnCode("RDB", DevNode, ret.rc) != 0);
|
|
|
|
return (u8)ret.value;
|
|
}
|
|
EXPORT_SYMBOL(iSeries_Read_Byte);
|
|
|
|
u16 iSeries_Read_Word(const volatile void __iomem *IoAddress)
|
|
{
|
|
u64 BarOffset;
|
|
u64 dsa;
|
|
struct HvCallPci_LoadReturn ret;
|
|
struct iSeries_Device_Node *DevNode =
|
|
xlate_iomm_address(IoAddress, &dsa, &BarOffset);
|
|
|
|
if (DevNode == NULL) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if ((jiffies - last_jiffies) > 60 * HZ) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR "iSeries_Read_Word: invalid access at IO address %p\n", IoAddress);
|
|
return 0xffff;
|
|
}
|
|
do {
|
|
++Pci_Io_Read_Count;
|
|
HvCall3Ret16(HvCallPciBarLoad16, &ret, dsa,
|
|
BarOffset, 0);
|
|
} while (CheckReturnCode("RDW", DevNode, ret.rc) != 0);
|
|
|
|
return swab16((u16)ret.value);
|
|
}
|
|
EXPORT_SYMBOL(iSeries_Read_Word);
|
|
|
|
u32 iSeries_Read_Long(const volatile void __iomem *IoAddress)
|
|
{
|
|
u64 BarOffset;
|
|
u64 dsa;
|
|
struct HvCallPci_LoadReturn ret;
|
|
struct iSeries_Device_Node *DevNode =
|
|
xlate_iomm_address(IoAddress, &dsa, &BarOffset);
|
|
|
|
if (DevNode == NULL) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if ((jiffies - last_jiffies) > 60 * HZ) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR "iSeries_Read_Long: invalid access at IO address %p\n", IoAddress);
|
|
return 0xffffffff;
|
|
}
|
|
do {
|
|
++Pci_Io_Read_Count;
|
|
HvCall3Ret16(HvCallPciBarLoad32, &ret, dsa,
|
|
BarOffset, 0);
|
|
} while (CheckReturnCode("RDL", DevNode, ret.rc) != 0);
|
|
|
|
return swab32((u32)ret.value);
|
|
}
|
|
EXPORT_SYMBOL(iSeries_Read_Long);
|
|
|
|
/*
|
|
* Write MM I/O Instructions for the iSeries
|
|
*
|
|
* iSeries_Write_Byte = Write Byte (8 bit)
|
|
* iSeries_Write_Word = Write Word(16 bit)
|
|
* iSeries_Write_Long = Write Long(32 bit)
|
|
*/
|
|
void iSeries_Write_Byte(u8 data, volatile void __iomem *IoAddress)
|
|
{
|
|
u64 BarOffset;
|
|
u64 dsa;
|
|
u64 rc;
|
|
struct iSeries_Device_Node *DevNode =
|
|
xlate_iomm_address(IoAddress, &dsa, &BarOffset);
|
|
|
|
if (DevNode == NULL) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if ((jiffies - last_jiffies) > 60 * HZ) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR "iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress);
|
|
return;
|
|
}
|
|
do {
|
|
++Pci_Io_Write_Count;
|
|
rc = HvCall4(HvCallPciBarStore8, dsa, BarOffset, data, 0);
|
|
} while (CheckReturnCode("WWB", DevNode, rc) != 0);
|
|
}
|
|
EXPORT_SYMBOL(iSeries_Write_Byte);
|
|
|
|
void iSeries_Write_Word(u16 data, volatile void __iomem *IoAddress)
|
|
{
|
|
u64 BarOffset;
|
|
u64 dsa;
|
|
u64 rc;
|
|
struct iSeries_Device_Node *DevNode =
|
|
xlate_iomm_address(IoAddress, &dsa, &BarOffset);
|
|
|
|
if (DevNode == NULL) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if ((jiffies - last_jiffies) > 60 * HZ) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR "iSeries_Write_Word: invalid access at IO address %p\n", IoAddress);
|
|
return;
|
|
}
|
|
do {
|
|
++Pci_Io_Write_Count;
|
|
rc = HvCall4(HvCallPciBarStore16, dsa, BarOffset, swab16(data), 0);
|
|
} while (CheckReturnCode("WWW", DevNode, rc) != 0);
|
|
}
|
|
EXPORT_SYMBOL(iSeries_Write_Word);
|
|
|
|
void iSeries_Write_Long(u32 data, volatile void __iomem *IoAddress)
|
|
{
|
|
u64 BarOffset;
|
|
u64 dsa;
|
|
u64 rc;
|
|
struct iSeries_Device_Node *DevNode =
|
|
xlate_iomm_address(IoAddress, &dsa, &BarOffset);
|
|
|
|
if (DevNode == NULL) {
|
|
static unsigned long last_jiffies;
|
|
static int num_printed;
|
|
|
|
if ((jiffies - last_jiffies) > 60 * HZ) {
|
|
last_jiffies = jiffies;
|
|
num_printed = 0;
|
|
}
|
|
if (num_printed++ < 10)
|
|
printk(KERN_ERR "iSeries_Write_Long: invalid access at IO address %p\n", IoAddress);
|
|
return;
|
|
}
|
|
do {
|
|
++Pci_Io_Write_Count;
|
|
rc = HvCall4(HvCallPciBarStore32, dsa, BarOffset, swab32(data), 0);
|
|
} while (CheckReturnCode("WWL", DevNode, rc) != 0);
|
|
}
|
|
EXPORT_SYMBOL(iSeries_Write_Long);
|