ba6d39256b
Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
839 lines
24 KiB
C
839 lines
24 KiB
C
/*
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* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _T4FW_RI_API_H_
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#define _T4FW_RI_API_H_
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#include "t4fw_api.h"
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enum fw_ri_wr_opcode {
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FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
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FW_RI_READ_REQ = 0x1,
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FW_RI_READ_RESP = 0x2,
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FW_RI_SEND = 0x3,
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FW_RI_SEND_WITH_INV = 0x4,
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FW_RI_SEND_WITH_SE = 0x5,
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FW_RI_SEND_WITH_SE_INV = 0x6,
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FW_RI_TERMINATE = 0x7,
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FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
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FW_RI_BIND_MW = 0x9,
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FW_RI_FAST_REGISTER = 0xa,
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FW_RI_LOCAL_INV = 0xb,
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FW_RI_QP_MODIFY = 0xc,
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FW_RI_BYPASS = 0xd,
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FW_RI_RECEIVE = 0xe,
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FW_RI_SGE_EC_CR_RETURN = 0xf
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};
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enum fw_ri_wr_flags {
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FW_RI_COMPLETION_FLAG = 0x01,
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FW_RI_NOTIFICATION_FLAG = 0x02,
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FW_RI_SOLICITED_EVENT_FLAG = 0x04,
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FW_RI_READ_FENCE_FLAG = 0x08,
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FW_RI_LOCAL_FENCE_FLAG = 0x10,
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FW_RI_RDMA_READ_INVALIDATE = 0x20
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};
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enum fw_ri_mpa_attrs {
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FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
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FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
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FW_RI_MPA_CRC_ENABLE = 0x04,
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FW_RI_MPA_IETF_ENABLE = 0x08
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};
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enum fw_ri_qp_caps {
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FW_RI_QP_RDMA_READ_ENABLE = 0x01,
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FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
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FW_RI_QP_BIND_ENABLE = 0x04,
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FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
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FW_RI_QP_STAG0_ENABLE = 0x10
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};
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enum fw_ri_addr_type {
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FW_RI_ZERO_BASED_TO = 0x00,
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FW_RI_VA_BASED_TO = 0x01
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};
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enum fw_ri_mem_perms {
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FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
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FW_RI_MEM_ACCESS_REM_READ = 0x02,
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FW_RI_MEM_ACCESS_REM = 0x03,
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FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
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FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
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FW_RI_MEM_ACCESS_LOCAL = 0x0C
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};
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enum fw_ri_stag_type {
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FW_RI_STAG_NSMR = 0x00,
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FW_RI_STAG_SMR = 0x01,
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FW_RI_STAG_MW = 0x02,
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FW_RI_STAG_MW_RELAXED = 0x03
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};
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enum fw_ri_data_op {
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FW_RI_DATA_IMMD = 0x81,
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FW_RI_DATA_DSGL = 0x82,
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FW_RI_DATA_ISGL = 0x83
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};
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enum fw_ri_sgl_depth {
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FW_RI_SGL_DEPTH_MAX_SQ = 16,
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FW_RI_SGL_DEPTH_MAX_RQ = 4
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};
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struct fw_ri_dsge_pair {
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__be32 len[2];
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__be64 addr[2];
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};
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struct fw_ri_dsgl {
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__u8 op;
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__u8 r1;
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__be16 nsge;
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__be32 len0;
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__be64 addr0;
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#ifndef C99_NOT_SUPPORTED
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struct fw_ri_dsge_pair sge[0];
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#endif
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};
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struct fw_ri_sge {
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__be32 stag;
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__be32 len;
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__be64 to;
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};
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struct fw_ri_isgl {
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__u8 op;
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__u8 r1;
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__be16 nsge;
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__be32 r2;
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#ifndef C99_NOT_SUPPORTED
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struct fw_ri_sge sge[0];
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#endif
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};
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struct fw_ri_immd {
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__u8 op;
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__u8 r1;
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__be16 r2;
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__be32 immdlen;
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#ifndef C99_NOT_SUPPORTED
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__u8 data[0];
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#endif
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};
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struct fw_ri_tpte {
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__be32 valid_to_pdid;
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__be32 locread_to_qpid;
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__be32 nosnoop_pbladdr;
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__be32 len_lo;
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__be32 va_hi;
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__be32 va_lo_fbo;
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__be32 dca_mwbcnt_pstag;
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__be32 len_hi;
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};
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#define S_FW_RI_TPTE_VALID 31
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#define M_FW_RI_TPTE_VALID 0x1
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#define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID)
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#define G_FW_RI_TPTE_VALID(x) \
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(((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
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#define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U)
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#define S_FW_RI_TPTE_STAGKEY 23
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#define M_FW_RI_TPTE_STAGKEY 0xff
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#define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY)
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#define G_FW_RI_TPTE_STAGKEY(x) \
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(((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
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#define S_FW_RI_TPTE_STAGSTATE 22
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#define M_FW_RI_TPTE_STAGSTATE 0x1
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#define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE)
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#define G_FW_RI_TPTE_STAGSTATE(x) \
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(((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
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#define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U)
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#define S_FW_RI_TPTE_STAGTYPE 20
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#define M_FW_RI_TPTE_STAGTYPE 0x3
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#define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE)
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#define G_FW_RI_TPTE_STAGTYPE(x) \
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(((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
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#define S_FW_RI_TPTE_PDID 0
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#define M_FW_RI_TPTE_PDID 0xfffff
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#define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID)
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#define G_FW_RI_TPTE_PDID(x) \
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(((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
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#define S_FW_RI_TPTE_PERM 28
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#define M_FW_RI_TPTE_PERM 0xf
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#define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM)
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#define G_FW_RI_TPTE_PERM(x) \
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(((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
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#define S_FW_RI_TPTE_REMINVDIS 27
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#define M_FW_RI_TPTE_REMINVDIS 0x1
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#define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS)
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#define G_FW_RI_TPTE_REMINVDIS(x) \
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(((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
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#define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U)
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#define S_FW_RI_TPTE_ADDRTYPE 26
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#define M_FW_RI_TPTE_ADDRTYPE 1
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#define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE)
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#define G_FW_RI_TPTE_ADDRTYPE(x) \
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(((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
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#define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U)
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#define S_FW_RI_TPTE_MWBINDEN 25
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#define M_FW_RI_TPTE_MWBINDEN 0x1
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#define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN)
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#define G_FW_RI_TPTE_MWBINDEN(x) \
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(((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
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#define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U)
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#define S_FW_RI_TPTE_PS 20
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#define M_FW_RI_TPTE_PS 0x1f
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#define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS)
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#define G_FW_RI_TPTE_PS(x) \
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(((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
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#define S_FW_RI_TPTE_QPID 0
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#define M_FW_RI_TPTE_QPID 0xfffff
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#define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID)
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#define G_FW_RI_TPTE_QPID(x) \
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(((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
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#define S_FW_RI_TPTE_NOSNOOP 30
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#define M_FW_RI_TPTE_NOSNOOP 0x1
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#define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP)
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#define G_FW_RI_TPTE_NOSNOOP(x) \
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(((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
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#define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U)
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#define S_FW_RI_TPTE_PBLADDR 0
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#define M_FW_RI_TPTE_PBLADDR 0x1fffffff
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#define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR)
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#define G_FW_RI_TPTE_PBLADDR(x) \
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(((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
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#define S_FW_RI_TPTE_DCA 24
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#define M_FW_RI_TPTE_DCA 0x1f
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#define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA)
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#define G_FW_RI_TPTE_DCA(x) \
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(((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
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#define S_FW_RI_TPTE_MWBCNT_PSTAG 0
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#define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff
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#define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
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((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
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#define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
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(((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
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enum fw_ri_res_type {
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FW_RI_RES_TYPE_SQ,
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FW_RI_RES_TYPE_RQ,
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FW_RI_RES_TYPE_CQ,
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};
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enum fw_ri_res_op {
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FW_RI_RES_OP_WRITE,
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FW_RI_RES_OP_RESET,
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};
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struct fw_ri_res {
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union fw_ri_restype {
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struct fw_ri_res_sqrq {
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__u8 restype;
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__u8 op;
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__be16 r3;
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__be32 eqid;
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__be32 r4[2];
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__be32 fetchszm_to_iqid;
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__be32 dcaen_to_eqsize;
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__be64 eqaddr;
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} sqrq;
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struct fw_ri_res_cq {
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__u8 restype;
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__u8 op;
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__be16 r3;
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__be32 iqid;
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__be32 r4[2];
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__be32 iqandst_to_iqandstindex;
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__be16 iqdroprss_to_iqesize;
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__be16 iqsize;
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__be64 iqaddr;
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__be32 iqns_iqro;
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__be32 r6_lo;
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__be64 r7;
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} cq;
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} u;
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};
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struct fw_ri_res_wr {
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__be32 op_nres;
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__be32 len16_pkd;
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__u64 cookie;
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#ifndef C99_NOT_SUPPORTED
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struct fw_ri_res res[0];
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#endif
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};
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#define S_FW_RI_RES_WR_NRES 0
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#define M_FW_RI_RES_WR_NRES 0xff
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#define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
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#define G_FW_RI_RES_WR_NRES(x) \
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(((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
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#define S_FW_RI_RES_WR_FETCHSZM 26
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#define M_FW_RI_RES_WR_FETCHSZM 0x1
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#define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM)
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#define G_FW_RI_RES_WR_FETCHSZM(x) \
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(((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
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#define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)
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#define S_FW_RI_RES_WR_STATUSPGNS 25
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#define M_FW_RI_RES_WR_STATUSPGNS 0x1
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#define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS)
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#define G_FW_RI_RES_WR_STATUSPGNS(x) \
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(((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
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#define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U)
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#define S_FW_RI_RES_WR_STATUSPGRO 24
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#define M_FW_RI_RES_WR_STATUSPGRO 0x1
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#define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO)
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#define G_FW_RI_RES_WR_STATUSPGRO(x) \
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(((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
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#define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U)
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#define S_FW_RI_RES_WR_FETCHNS 23
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#define M_FW_RI_RES_WR_FETCHNS 0x1
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#define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS)
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#define G_FW_RI_RES_WR_FETCHNS(x) \
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(((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
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#define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U)
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#define S_FW_RI_RES_WR_FETCHRO 22
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#define M_FW_RI_RES_WR_FETCHRO 0x1
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#define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO)
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#define G_FW_RI_RES_WR_FETCHRO(x) \
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(((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
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#define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U)
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#define S_FW_RI_RES_WR_HOSTFCMODE 20
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#define M_FW_RI_RES_WR_HOSTFCMODE 0x3
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#define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE)
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#define G_FW_RI_RES_WR_HOSTFCMODE(x) \
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(((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
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#define S_FW_RI_RES_WR_CPRIO 19
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#define M_FW_RI_RES_WR_CPRIO 0x1
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#define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)
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#define G_FW_RI_RES_WR_CPRIO(x) \
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(((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
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#define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U)
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#define S_FW_RI_RES_WR_ONCHIP 18
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#define M_FW_RI_RES_WR_ONCHIP 0x1
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#define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP)
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#define G_FW_RI_RES_WR_ONCHIP(x) \
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(((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
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#define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U)
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#define S_FW_RI_RES_WR_PCIECHN 16
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#define M_FW_RI_RES_WR_PCIECHN 0x3
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#define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN)
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#define G_FW_RI_RES_WR_PCIECHN(x) \
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(((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
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#define S_FW_RI_RES_WR_IQID 0
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#define M_FW_RI_RES_WR_IQID 0xffff
|
|
#define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID)
|
|
#define G_FW_RI_RES_WR_IQID(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
|
|
|
|
#define S_FW_RI_RES_WR_DCAEN 31
|
|
#define M_FW_RI_RES_WR_DCAEN 0x1
|
|
#define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)
|
|
#define G_FW_RI_RES_WR_DCAEN(x) \
|
|
(((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
|
|
#define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U)
|
|
|
|
#define S_FW_RI_RES_WR_DCACPU 26
|
|
#define M_FW_RI_RES_WR_DCACPU 0x1f
|
|
#define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU)
|
|
#define G_FW_RI_RES_WR_DCACPU(x) \
|
|
(((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
|
|
|
|
#define S_FW_RI_RES_WR_FBMIN 23
|
|
#define M_FW_RI_RES_WR_FBMIN 0x7
|
|
#define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)
|
|
#define G_FW_RI_RES_WR_FBMIN(x) \
|
|
(((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
|
|
|
|
#define S_FW_RI_RES_WR_FBMAX 20
|
|
#define M_FW_RI_RES_WR_FBMAX 0x7
|
|
#define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)
|
|
#define G_FW_RI_RES_WR_FBMAX(x) \
|
|
(((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
|
|
|
|
#define S_FW_RI_RES_WR_CIDXFTHRESHO 19
|
|
#define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1
|
|
#define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
|
|
#define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
|
|
(((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
|
|
#define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
|
|
|
|
#define S_FW_RI_RES_WR_CIDXFTHRESH 16
|
|
#define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
|
|
#define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
|
|
#define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
|
|
(((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
|
|
|
|
#define S_FW_RI_RES_WR_EQSIZE 0
|
|
#define M_FW_RI_RES_WR_EQSIZE 0xffff
|
|
#define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE)
|
|
#define G_FW_RI_RES_WR_EQSIZE(x) \
|
|
(((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
|
|
|
|
#define S_FW_RI_RES_WR_IQANDST 15
|
|
#define M_FW_RI_RES_WR_IQANDST 0x1
|
|
#define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST)
|
|
#define G_FW_RI_RES_WR_IQANDST(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
|
|
#define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQANUS 14
|
|
#define M_FW_RI_RES_WR_IQANUS 0x1
|
|
#define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS)
|
|
#define G_FW_RI_RES_WR_IQANUS(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
|
|
#define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQANUD 12
|
|
#define M_FW_RI_RES_WR_IQANUD 0x3
|
|
#define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD)
|
|
#define G_FW_RI_RES_WR_IQANUD(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
|
|
|
|
#define S_FW_RI_RES_WR_IQANDSTINDEX 0
|
|
#define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff
|
|
#define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
|
|
#define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
|
|
|
|
#define S_FW_RI_RES_WR_IQDROPRSS 15
|
|
#define M_FW_RI_RES_WR_IQDROPRSS 0x1
|
|
#define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS)
|
|
#define G_FW_RI_RES_WR_IQDROPRSS(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
|
|
#define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQGTSMODE 14
|
|
#define M_FW_RI_RES_WR_IQGTSMODE 0x1
|
|
#define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE)
|
|
#define G_FW_RI_RES_WR_IQGTSMODE(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
|
|
#define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQPCIECH 12
|
|
#define M_FW_RI_RES_WR_IQPCIECH 0x3
|
|
#define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH)
|
|
#define G_FW_RI_RES_WR_IQPCIECH(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
|
|
|
|
#define S_FW_RI_RES_WR_IQDCAEN 11
|
|
#define M_FW_RI_RES_WR_IQDCAEN 0x1
|
|
#define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN)
|
|
#define G_FW_RI_RES_WR_IQDCAEN(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
|
|
#define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQDCACPU 6
|
|
#define M_FW_RI_RES_WR_IQDCACPU 0x1f
|
|
#define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU)
|
|
#define G_FW_RI_RES_WR_IQDCACPU(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
|
|
|
|
#define S_FW_RI_RES_WR_IQINTCNTTHRESH 4
|
|
#define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3
|
|
#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
|
|
((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
|
|
#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
|
|
|
|
#define S_FW_RI_RES_WR_IQO 3
|
|
#define M_FW_RI_RES_WR_IQO 0x1
|
|
#define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO)
|
|
#define G_FW_RI_RES_WR_IQO(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
|
|
#define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQCPRIO 2
|
|
#define M_FW_RI_RES_WR_IQCPRIO 0x1
|
|
#define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO)
|
|
#define G_FW_RI_RES_WR_IQCPRIO(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
|
|
#define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQESIZE 0
|
|
#define M_FW_RI_RES_WR_IQESIZE 0x3
|
|
#define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE)
|
|
#define G_FW_RI_RES_WR_IQESIZE(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
|
|
|
|
#define S_FW_RI_RES_WR_IQNS 31
|
|
#define M_FW_RI_RES_WR_IQNS 0x1
|
|
#define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS)
|
|
#define G_FW_RI_RES_WR_IQNS(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
|
|
#define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U)
|
|
|
|
#define S_FW_RI_RES_WR_IQRO 30
|
|
#define M_FW_RI_RES_WR_IQRO 0x1
|
|
#define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO)
|
|
#define G_FW_RI_RES_WR_IQRO(x) \
|
|
(((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
|
|
#define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U)
|
|
|
|
struct fw_ri_rdma_write_wr {
|
|
__u8 opcode;
|
|
__u8 flags;
|
|
__u16 wrid;
|
|
__u8 r1[3];
|
|
__u8 len16;
|
|
__be64 r2;
|
|
__be32 plen;
|
|
__be32 stag_sink;
|
|
__be64 to_sink;
|
|
#ifndef C99_NOT_SUPPORTED
|
|
union {
|
|
struct fw_ri_immd immd_src[0];
|
|
struct fw_ri_isgl isgl_src[0];
|
|
} u;
|
|
#endif
|
|
};
|
|
|
|
struct fw_ri_send_wr {
|
|
__u8 opcode;
|
|
__u8 flags;
|
|
__u16 wrid;
|
|
__u8 r1[3];
|
|
__u8 len16;
|
|
__be32 sendop_pkd;
|
|
__be32 stag_inv;
|
|
__be32 plen;
|
|
__be32 r3;
|
|
__be64 r4;
|
|
#ifndef C99_NOT_SUPPORTED
|
|
union {
|
|
struct fw_ri_immd immd_src[0];
|
|
struct fw_ri_isgl isgl_src[0];
|
|
} u;
|
|
#endif
|
|
};
|
|
|
|
#define S_FW_RI_SEND_WR_SENDOP 0
|
|
#define M_FW_RI_SEND_WR_SENDOP 0xf
|
|
#define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP)
|
|
#define G_FW_RI_SEND_WR_SENDOP(x) \
|
|
(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
|
|
|
|
struct fw_ri_rdma_read_wr {
|
|
__u8 opcode;
|
|
__u8 flags;
|
|
__u16 wrid;
|
|
__u8 r1[3];
|
|
__u8 len16;
|
|
__be64 r2;
|
|
__be32 stag_sink;
|
|
__be32 to_sink_hi;
|
|
__be32 to_sink_lo;
|
|
__be32 plen;
|
|
__be32 stag_src;
|
|
__be32 to_src_hi;
|
|
__be32 to_src_lo;
|
|
__be32 r5;
|
|
};
|
|
|
|
struct fw_ri_recv_wr {
|
|
__u8 opcode;
|
|
__u8 r1;
|
|
__u16 wrid;
|
|
__u8 r2[3];
|
|
__u8 len16;
|
|
struct fw_ri_isgl isgl;
|
|
};
|
|
|
|
struct fw_ri_bind_mw_wr {
|
|
__u8 opcode;
|
|
__u8 flags;
|
|
__u16 wrid;
|
|
__u8 r1[3];
|
|
__u8 len16;
|
|
__u8 qpbinde_to_dcacpu;
|
|
__u8 pgsz_shift;
|
|
__u8 addr_type;
|
|
__u8 mem_perms;
|
|
__be32 stag_mr;
|
|
__be32 stag_mw;
|
|
__be32 r3;
|
|
__be64 len_mw;
|
|
__be64 va_fbo;
|
|
__be64 r4;
|
|
};
|
|
|
|
#define S_FW_RI_BIND_MW_WR_QPBINDE 6
|
|
#define M_FW_RI_BIND_MW_WR_QPBINDE 0x1
|
|
#define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
|
|
#define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
|
|
(((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
|
|
#define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U)
|
|
|
|
#define S_FW_RI_BIND_MW_WR_NS 5
|
|
#define M_FW_RI_BIND_MW_WR_NS 0x1
|
|
#define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS)
|
|
#define G_FW_RI_BIND_MW_WR_NS(x) \
|
|
(((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
|
|
#define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U)
|
|
|
|
#define S_FW_RI_BIND_MW_WR_DCACPU 0
|
|
#define M_FW_RI_BIND_MW_WR_DCACPU 0x1f
|
|
#define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU)
|
|
#define G_FW_RI_BIND_MW_WR_DCACPU(x) \
|
|
(((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
|
|
|
|
struct fw_ri_fr_nsmr_wr {
|
|
__u8 opcode;
|
|
__u8 flags;
|
|
__u16 wrid;
|
|
__u8 r1[3];
|
|
__u8 len16;
|
|
__u8 qpbinde_to_dcacpu;
|
|
__u8 pgsz_shift;
|
|
__u8 addr_type;
|
|
__u8 mem_perms;
|
|
__be32 stag;
|
|
__be32 len_hi;
|
|
__be32 len_lo;
|
|
__be32 va_hi;
|
|
__be32 va_lo_fbo;
|
|
};
|
|
|
|
#define S_FW_RI_FR_NSMR_WR_QPBINDE 6
|
|
#define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1
|
|
#define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
|
|
#define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
|
|
(((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
|
|
#define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
|
|
|
|
#define S_FW_RI_FR_NSMR_WR_NS 5
|
|
#define M_FW_RI_FR_NSMR_WR_NS 0x1
|
|
#define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS)
|
|
#define G_FW_RI_FR_NSMR_WR_NS(x) \
|
|
(((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
|
|
#define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U)
|
|
|
|
#define S_FW_RI_FR_NSMR_WR_DCACPU 0
|
|
#define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f
|
|
#define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
|
|
#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
|
|
(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
|
|
|
|
struct fw_ri_inv_lstag_wr {
|
|
__u8 opcode;
|
|
__u8 flags;
|
|
__u16 wrid;
|
|
__u8 r1[3];
|
|
__u8 len16;
|
|
__be32 r2;
|
|
__be32 stag_inv;
|
|
};
|
|
|
|
enum fw_ri_type {
|
|
FW_RI_TYPE_INIT,
|
|
FW_RI_TYPE_FINI,
|
|
FW_RI_TYPE_TERMINATE
|
|
};
|
|
|
|
enum fw_ri_init_p2ptype {
|
|
FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
|
|
FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
|
|
FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
|
|
FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
|
|
FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
|
|
FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
|
|
FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
|
|
};
|
|
|
|
struct fw_ri_wr {
|
|
__be32 op_compl;
|
|
__be32 flowid_len16;
|
|
__u64 cookie;
|
|
union fw_ri {
|
|
struct fw_ri_init {
|
|
__u8 type;
|
|
__u8 mpareqbit_p2ptype;
|
|
__u8 r4[2];
|
|
__u8 mpa_attrs;
|
|
__u8 qp_caps;
|
|
__be16 nrqe;
|
|
__be32 pdid;
|
|
__be32 qpid;
|
|
__be32 sq_eqid;
|
|
__be32 rq_eqid;
|
|
__be32 scqid;
|
|
__be32 rcqid;
|
|
__be32 ord_max;
|
|
__be32 ird_max;
|
|
__be32 iss;
|
|
__be32 irs;
|
|
__be32 hwrqsize;
|
|
__be32 hwrqaddr;
|
|
__be64 r5;
|
|
union fw_ri_init_p2p {
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struct fw_ri_rdma_write_wr write;
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struct fw_ri_rdma_read_wr read;
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|
struct fw_ri_send_wr send;
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|
} u;
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|
} init;
|
|
struct fw_ri_fini {
|
|
__u8 type;
|
|
__u8 r3[7];
|
|
__be64 r4;
|
|
} fini;
|
|
struct fw_ri_terminate {
|
|
__u8 type;
|
|
__u8 r3[3];
|
|
__be32 immdlen;
|
|
__u8 termmsg[40];
|
|
} terminate;
|
|
} u;
|
|
};
|
|
|
|
#define S_FW_RI_WR_MPAREQBIT 7
|
|
#define M_FW_RI_WR_MPAREQBIT 0x1
|
|
#define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)
|
|
#define G_FW_RI_WR_MPAREQBIT(x) \
|
|
(((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
|
|
#define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U)
|
|
|
|
#define S_FW_RI_WR_P2PTYPE 0
|
|
#define M_FW_RI_WR_P2PTYPE 0xf
|
|
#define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE)
|
|
#define G_FW_RI_WR_P2PTYPE(x) \
|
|
(((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
|
|
|
|
struct tcp_options {
|
|
__be16 mss;
|
|
__u8 wsf;
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
|
__u8:4;
|
|
__u8 unknown:1;
|
|
__u8:1;
|
|
__u8 sack:1;
|
|
__u8 tstamp:1;
|
|
#else
|
|
__u8 tstamp:1;
|
|
__u8 sack:1;
|
|
__u8:1;
|
|
__u8 unknown:1;
|
|
__u8:4;
|
|
#endif
|
|
};
|
|
|
|
struct cpl_pass_accept_req {
|
|
union opcode_tid ot;
|
|
__be16 rsvd;
|
|
__be16 len;
|
|
__be32 hdr_len;
|
|
__be16 vlan;
|
|
__be16 l2info;
|
|
__be32 tos_stid;
|
|
struct tcp_options tcpopt;
|
|
};
|
|
|
|
/* cpl_pass_accept_req.hdr_len fields */
|
|
#define S_SYN_RX_CHAN 0
|
|
#define M_SYN_RX_CHAN 0xF
|
|
#define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
|
|
#define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
|
|
|
|
#define S_TCP_HDR_LEN 10
|
|
#define M_TCP_HDR_LEN 0x3F
|
|
#define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
|
|
#define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
|
|
|
|
#define S_IP_HDR_LEN 16
|
|
#define M_IP_HDR_LEN 0x3FF
|
|
#define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
|
|
#define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
|
|
|
|
#define S_ETH_HDR_LEN 26
|
|
#define M_ETH_HDR_LEN 0x1F
|
|
#define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
|
|
#define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
|
|
|
|
/* cpl_pass_accept_req.l2info fields */
|
|
#define S_SYN_MAC_IDX 0
|
|
#define M_SYN_MAC_IDX 0x1FF
|
|
#define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
|
|
#define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
|
|
|
|
#define S_SYN_XACT_MATCH 9
|
|
#define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
|
|
#define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
|
|
|
|
#define S_SYN_INTF 12
|
|
#define M_SYN_INTF 0xF
|
|
#define V_SYN_INTF(x) ((x) << S_SYN_INTF)
|
|
#define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
|
|
|
|
struct ulptx_idata {
|
|
__be32 cmd_more;
|
|
__be32 len;
|
|
};
|
|
|
|
#define S_ULPTX_NSGE 0
|
|
#define M_ULPTX_NSGE 0xFFFF
|
|
#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
|
|
|
|
#define S_RX_DACK_MODE 29
|
|
#define M_RX_DACK_MODE 0x3
|
|
#define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
|
|
#define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
|
|
|
|
#define S_RX_DACK_CHANGE 31
|
|
#define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
|
|
#define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
|
|
|
|
#endif /* _T4FW_RI_API_H_ */
|