b9d4d42ad9
This patch removes the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition for ARMv5 and earlier processors. On such processors, the context switch requires a full cache flush. To avoid high interrupt latencies, this patch defers the mm switching to the post-lock switch hook if the interrupts are disabled. Reviewed-by: Will Deacon <will.deacon@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com> Tested-by: Marc Zyngier <Marc.Zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
191 lines
5 KiB
C
191 lines
5 KiB
C
/*
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* arch/arm/include/asm/mmu_context.h
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*
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* Copyright (C) 1996 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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* 27-06-1996 RMK Created
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*/
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#ifndef __ASM_ARM_MMU_CONTEXT_H
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#define __ASM_ARM_MMU_CONTEXT_H
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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void __check_kvm_seq(struct mm_struct *mm);
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#ifdef CONFIG_CPU_HAS_ASID
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/*
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* On ARMv6, we have the following structure in the Context ID:
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*
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* 31 7 0
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* +-------------------------+-----------+
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* | process ID | ASID |
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* +-------------------------+-----------+
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* | context ID |
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* +-------------------------------------+
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*
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* The ASID is used to tag entries in the CPU caches and TLBs.
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* The context ID is used by debuggers and trace logic, and
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* should be unique within all running processes.
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*/
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#define ASID_BITS 8
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#define ASID_MASK ((~0) << ASID_BITS)
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#define ASID_FIRST_VERSION (1 << ASID_BITS)
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extern unsigned int cpu_last_asid;
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void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void __new_context(struct mm_struct *mm);
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void cpu_set_reserved_ttbr0(void);
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static inline void switch_new_context(struct mm_struct *mm)
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{
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unsigned long flags;
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__new_context(mm);
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local_irq_save(flags);
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cpu_switch_mm(mm->pgd, mm);
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local_irq_restore(flags);
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}
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static inline void check_and_switch_context(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
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__check_kvm_seq(mm);
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/*
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* Required during context switch to avoid speculative page table
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* walking with the wrong TTBR.
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*/
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cpu_set_reserved_ttbr0();
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if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
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/*
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* The ASID is from the current generation, just switch to the
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* new pgd. This condition is only true for calls from
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* context_switch() and interrupts are already disabled.
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*/
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cpu_switch_mm(mm->pgd, mm);
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else if (irqs_disabled())
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/*
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* Defer the new ASID allocation until after the context
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* switch critical region since __new_context() cannot be
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* called with interrupts disabled (it sends IPIs).
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*/
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set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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else
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/*
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* That is a direct call to switch_mm() or activate_mm() with
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* interrupts enabled and a new context.
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*/
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switch_new_context(mm);
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}
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#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
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#define finish_arch_post_lock_switch \
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finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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if (test_and_clear_thread_flag(TIF_SWITCH_MM))
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switch_new_context(current->mm);
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}
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#else /* !CONFIG_CPU_HAS_ASID */
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#ifdef CONFIG_MMU
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static inline void check_and_switch_context(struct mm_struct *mm,
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struct task_struct *tsk)
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{
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if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
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__check_kvm_seq(mm);
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if (irqs_disabled())
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/*
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* cpu_switch_mm() needs to flush the VIVT caches. To avoid
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* high interrupt latencies, defer the call and continue
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* running with the old mm. Since we only support UP systems
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* on non-ASID CPUs, the old mm will remain valid until the
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* finish_arch_post_lock_switch() call.
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*/
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set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
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else
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cpu_switch_mm(mm->pgd, mm);
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}
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#define finish_arch_post_lock_switch \
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finish_arch_post_lock_switch
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static inline void finish_arch_post_lock_switch(void)
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{
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if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
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struct mm_struct *mm = current->mm;
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cpu_switch_mm(mm->pgd, mm);
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}
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}
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#endif /* CONFIG_MMU */
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#define init_new_context(tsk,mm) 0
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#endif /* CONFIG_CPU_HAS_ASID */
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#define destroy_context(mm) do { } while(0)
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/*
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* This is called when "tsk" is about to enter lazy TLB mode.
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*
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* mm: describes the currently active mm context
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* tsk: task which is entering lazy tlb
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* cpu: cpu number which is entering lazy tlb
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*
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* tsk->mm will be NULL
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*/
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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#ifdef CONFIG_MMU
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unsigned int cpu = smp_processor_id();
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#ifdef CONFIG_SMP
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/* check for possible thread migration */
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if (!cpumask_empty(mm_cpumask(next)) &&
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!cpumask_test_cpu(cpu, mm_cpumask(next)))
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__flush_icache_all();
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#endif
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if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
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check_and_switch_context(next, tsk);
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if (cache_is_vivt())
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cpumask_clear_cpu(cpu, mm_cpumask(prev));
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}
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#endif
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, NULL)
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#endif
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