4319503779
Some atom procs don't do freq scaling (such as the atom 330 on my own littlefalls2 board). By adding the atom family here, we at least get the benefit of passive cooling in a thermal emergency. Not sure how to see that its actually helping any, but the driver does bind and claim its functioning on my atom 330. Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Dave Jones <davej@redhat.com>
337 lines
8.4 KiB
C
337 lines
8.4 KiB
C
/*
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* Pentium 4/Xeon CPU on demand clock modulation/speed scaling
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* (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
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* (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
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* (C) 2002 Arjan van de Ven <arjanv@redhat.com>
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* (C) 2002 Tora T. Engstad
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* The author(s) of this software shall not be held liable for damages
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* of any nature resulting due to the use of this software. This
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* software is provided AS-IS with no warranties.
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*
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* Date Errata Description
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* 20020525 N44, O17 12.5% or 25% DC causes lockup
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/cpufreq.h>
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#include <linux/slab.h>
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#include <linux/cpumask.h>
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#include <linux/timex.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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#include <asm/timer.h>
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#include "speedstep-lib.h"
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#define PFX "p4-clockmod: "
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
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"p4-clockmod", msg)
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/*
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* Duty Cycle (3bits), note DC_DISABLE is not specified in
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* intel docs i just use it to mean disable
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*/
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enum {
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DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
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DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
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};
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#define DC_ENTRIES 8
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static int has_N44_O17_errata[NR_CPUS];
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static unsigned int stock_freq;
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static struct cpufreq_driver p4clockmod_driver;
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static unsigned int cpufreq_p4_get(unsigned int cpu);
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static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
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{
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u32 l, h;
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if (!cpu_online(cpu) ||
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(newstate > DC_DISABLE) || (newstate == DC_RESV))
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return -EINVAL;
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rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);
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if (l & 0x01)
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dprintk("CPU#%d currently thermal throttled\n", cpu);
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if (has_N44_O17_errata[cpu] &&
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(newstate == DC_25PT || newstate == DC_DFLT))
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newstate = DC_38PT;
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rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
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if (newstate == DC_DISABLE) {
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dprintk("CPU#%d disabling modulation\n", cpu);
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wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
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} else {
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dprintk("CPU#%d setting duty cycle to %d%%\n",
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cpu, ((125 * newstate) / 10));
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/* bits 63 - 5 : reserved
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* bit 4 : enable/disable
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* bits 3-1 : duty cycle
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* bit 0 : reserved
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*/
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l = (l & ~14);
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l = l | (1<<4) | ((newstate & 0x7)<<1);
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wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
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}
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return 0;
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}
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static struct cpufreq_frequency_table p4clockmod_table[] = {
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{DC_RESV, CPUFREQ_ENTRY_INVALID},
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{DC_DFLT, 0},
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{DC_25PT, 0},
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{DC_38PT, 0},
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{DC_50PT, 0},
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{DC_64PT, 0},
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{DC_75PT, 0},
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{DC_88PT, 0},
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{DC_DISABLE, 0},
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{DC_RESV, CPUFREQ_TABLE_END},
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};
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static int cpufreq_p4_target(struct cpufreq_policy *policy,
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unsigned int target_freq,
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unsigned int relation)
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{
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unsigned int newstate = DC_RESV;
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struct cpufreq_freqs freqs;
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int i;
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if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0],
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target_freq, relation, &newstate))
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return -EINVAL;
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freqs.old = cpufreq_p4_get(policy->cpu);
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freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
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if (freqs.new == freqs.old)
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return 0;
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/* notifiers */
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for_each_cpu(i, policy->cpus) {
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freqs.cpu = i;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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}
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/* run on each logical CPU,
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* see section 13.15.3 of IA32 Intel Architecture Software
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* Developer's Manual, Volume 3
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*/
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for_each_cpu(i, policy->cpus)
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cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
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/* notifiers */
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for_each_cpu(i, policy->cpus) {
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freqs.cpu = i;
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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}
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return 0;
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}
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static int cpufreq_p4_verify(struct cpufreq_policy *policy)
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{
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return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
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}
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static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
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{
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if (c->x86 == 0x06) {
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if (cpu_has(c, X86_FEATURE_EST))
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printk(KERN_WARNING PFX "Warning: EST-capable CPU "
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"detected. The acpi-cpufreq module offers "
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"voltage scaling in addition of frequency "
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"scaling. You should use that instead of "
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"p4-clockmod, if possible.\n");
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switch (c->x86_model) {
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case 0x0E: /* Core */
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case 0x0F: /* Core Duo */
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case 0x16: /* Celeron Core */
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case 0x1C: /* Atom */
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p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
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return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
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case 0x0D: /* Pentium M (Dothan) */
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p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
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/* fall through */
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case 0x09: /* Pentium M (Banias) */
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return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
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}
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}
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if (c->x86 != 0xF) {
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if (!cpu_has(c, X86_FEATURE_EST))
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printk(KERN_WARNING PFX "Unknown CPU. "
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"Please send an e-mail to "
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"<cpufreq@vger.kernel.org>\n");
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return 0;
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}
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/* on P-4s, the TSC runs with constant frequency independent whether
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* throttling is active or not. */
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p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
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if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) {
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printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
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"The speedstep-ich or acpi cpufreq modules offer "
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"voltage scaling in addition of frequency scaling. "
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"You should use either one instead of p4-clockmod, "
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"if possible.\n");
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return speedstep_get_frequency(SPEEDSTEP_CPU_P4M);
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}
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return speedstep_get_frequency(SPEEDSTEP_CPU_P4D);
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}
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static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
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{
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struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
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int cpuid = 0;
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unsigned int i;
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#ifdef CONFIG_SMP
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cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
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#endif
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/* Errata workaround */
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cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
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switch (cpuid) {
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case 0x0f07:
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case 0x0f0a:
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case 0x0f11:
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case 0x0f12:
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has_N44_O17_errata[policy->cpu] = 1;
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dprintk("has errata -- disabling low frequencies\n");
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}
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if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D &&
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c->x86_model < 2) {
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/* switch to maximum frequency and measure result */
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cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
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recalibrate_cpu_khz();
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}
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/* get max frequency */
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stock_freq = cpufreq_p4_get_frequency(c);
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if (!stock_freq)
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return -EINVAL;
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/* table init */
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for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
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if ((i < 2) && (has_N44_O17_errata[policy->cpu]))
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p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
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else
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p4clockmod_table[i].frequency = (stock_freq * i)/8;
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}
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cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
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/* cpuinfo and default policy values */
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/* the transition latency is set to be 1 higher than the maximum
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* transition latency of the ondemand governor */
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policy->cpuinfo.transition_latency = 10000001;
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policy->cur = stock_freq;
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return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
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}
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static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
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{
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cpufreq_frequency_table_put_attr(policy->cpu);
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return 0;
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}
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static unsigned int cpufreq_p4_get(unsigned int cpu)
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{
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u32 l, h;
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rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
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if (l & 0x10) {
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l = l >> 1;
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l &= 0x7;
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} else
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l = DC_DISABLE;
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if (l != DC_DISABLE)
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return stock_freq * l / 8;
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return stock_freq;
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}
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static struct freq_attr *p4clockmod_attr[] = {
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&cpufreq_freq_attr_scaling_available_freqs,
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NULL,
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};
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static struct cpufreq_driver p4clockmod_driver = {
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.verify = cpufreq_p4_verify,
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.target = cpufreq_p4_target,
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.init = cpufreq_p4_cpu_init,
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.exit = cpufreq_p4_cpu_exit,
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.get = cpufreq_p4_get,
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.name = "p4-clockmod",
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.owner = THIS_MODULE,
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.attr = p4clockmod_attr,
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};
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static int __init cpufreq_p4_init(void)
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{
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struct cpuinfo_x86 *c = &cpu_data(0);
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int ret;
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/*
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* THERM_CONTROL is architectural for IA32 now, so
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* we can rely on the capability checks
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*/
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if (c->x86_vendor != X86_VENDOR_INTEL)
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return -ENODEV;
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if (!test_cpu_cap(c, X86_FEATURE_ACPI) ||
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!test_cpu_cap(c, X86_FEATURE_ACC))
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return -ENODEV;
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ret = cpufreq_register_driver(&p4clockmod_driver);
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if (!ret)
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printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock "
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"Modulation available\n");
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return ret;
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}
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static void __exit cpufreq_p4_exit(void)
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{
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cpufreq_unregister_driver(&p4clockmod_driver);
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}
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MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
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MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
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MODULE_LICENSE("GPL");
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late_initcall(cpufreq_p4_init);
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module_exit(cpufreq_p4_exit);
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