6cb971114f
Use the simple-bus node to discover the io area, and remap the cached and bypass io ranges. The parent-bus-address value of the first triplet in the "ranges" property is used. This value is rounded down to the nearest 256MB boundary. The length of the io area is fixed at 256MB; the "ranges" property length value is ignored. Other limitations: (1) only the first simple-bus node is considered, and (2) only the first triplet of the "ranges" property is considered. See ePAPR 1.1 §6.5 for the simple-bus node description, and §2.3.8 for the "ranges" property description. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
163 lines
3.3 KiB
C
163 lines
3.3 KiB
C
/*
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* arch/xtensa/include/asm/initialize_mmu.h
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*
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* Initializes MMU:
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*
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* For the new V3 MMU we remap the TLB from virtual == physical
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* to the standard Linux mapping used in earlier MMU's.
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*
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* The the MMU we also support a new configuration register that
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* specifies how the S32C1I instruction operates with the cache
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* controller.
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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* Copyright (C) 2008 - 2012 Tensilica, Inc.
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*
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* Marc Gauthier <marc@tensilica.com>
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* Pete Delaney <piet@tensilica.com>
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*/
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#ifndef _XTENSA_INITIALIZE_MMU_H
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#define _XTENSA_INITIALIZE_MMU_H
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#include <asm/pgtable.h>
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#include <asm/vectors.h>
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#define CA_BYPASS (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
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#define CA_WRITEBACK (_PAGE_CA_WB | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
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#ifdef __ASSEMBLY__
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#define XTENSA_HWVERSION_RC_2009_0 230000
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.macro initialize_mmu
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#if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
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/*
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* We Have Atomic Operation Control (ATOMCTL) Register; Initialize it.
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* For details see Documentation/xtensa/atomctl.txt
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*/
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#if XCHAL_DCACHE_IS_COHERENT
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movi a3, 0x25 /* For SMP/MX -- internal for writeback,
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* RCW otherwise
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*/
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#else
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movi a3, 0x29 /* non-MX -- Most cores use Std Memory
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* Controlers which usually can't use RCW
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*/
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#endif
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wsr a3, atomctl
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#endif /* XCHAL_HAVE_S32C1I &&
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* (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
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*/
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#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
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/*
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* Have MMU v3
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*/
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#if !XCHAL_HAVE_VECBASE
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# error "MMU v3 requires reloc vectors"
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#endif
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movi a1, 0
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_call0 1f
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_j 2f
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.align 4
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1: movi a2, 0x10000000
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movi a3, 0x18000000
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add a2, a2, a0
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9: bgeu a2, a3, 9b /* PC is out of the expected range */
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/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
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movi a2, 0x40000006
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idtlb a2
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iitlb a2
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isync
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/* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
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* and jump to the new mapping.
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*/
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srli a3, a0, 27
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slli a3, a3, 27
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addi a3, a3, CA_BYPASS
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addi a7, a2, -1
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wdtlb a3, a7
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witlb a3, a7
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isync
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slli a4, a0, 5
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srli a4, a4, 5
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addi a5, a2, -6
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add a4, a4, a5
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jx a4
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/* Step 3: unmap everything other than current area.
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* Start at 0x60000000, wrap around, and end with 0x20000000
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*/
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2: movi a4, 0x20000000
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add a5, a2, a4
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3: idtlb a5
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iitlb a5
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add a5, a5, a4
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bne a5, a2, 3b
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/* Step 4: Setup MMU with the old V2 mappings. */
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movi a6, 0x01000000
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wsr a6, ITLBCFG
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wsr a6, DTLBCFG
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isync
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movi a5, 0xd0000005
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movi a4, CA_WRITEBACK
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wdtlb a4, a5
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witlb a4, a5
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movi a5, 0xd8000005
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movi a4, CA_BYPASS
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wdtlb a4, a5
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witlb a4, a5
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movi a5, XCHAL_KIO_CACHED_VADDR + 6
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movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_WRITEBACK
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wdtlb a4, a5
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witlb a4, a5
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movi a5, XCHAL_KIO_BYPASS_VADDR + 6
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movi a4, XCHAL_KIO_DEFAULT_PADDR + CA_BYPASS
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wdtlb a4, a5
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witlb a4, a5
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isync
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/* Jump to self, using MMU v2 mappings. */
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movi a4, 1f
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jx a4
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1:
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movi a2, VECBASE_RESET_VADDR
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wsr a2, vecbase
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/* Step 5: remove temporary mapping. */
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idtlb a7
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iitlb a7
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isync
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movi a0, 0
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wsr a0, ptevaddr
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rsync
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#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
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XCHAL_HAVE_SPANNING_WAY */
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.endm
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#endif /*__ASSEMBLY__*/
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#endif /* _XTENSA_INITIALIZE_MMU_H */
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