d552920a02
This is a power gating idle mode. It support power gating vdd_cpu rail after all cpu cores in "powered-down" status. For Tegra30, the CPU0 can enter this state only when all secondary CPU is offline. We need to take care and make sure whole secondary CPUs were offline and checking the CPU power gate status. After that, the CPU0 can go into "powered-down" state safely. Then shut off the CPU rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Base on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/*
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* Copyright (C) 2010 Google, Inc.
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* Copyright (c) 2010-2012 NVIDIA Corporation. All rights reserved.
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MACH_TEGRA_PM_H_
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#define _MACH_TEGRA_PM_H_
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void save_cpu_arch_register(void);
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void restore_cpu_arch_register(void);
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void tegra_clear_cpu_in_lp2(int phy_cpu_id);
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bool tegra_set_cpu_in_lp2(int phy_cpu_id);
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void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time);
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extern void (*tegra_tear_down_cpu)(void);
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#endif /* _MACH_TEGRA_PM_H_ */
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