5c334eed6e
Using device_initcall makes it happen for every platform that compiles this file in. This is really bad, for obvious reasons. Instead, we use the .init field of the machine description. If the platform needs the hook to do something specific it can provides its own function and call mpc52xx_declare_of_platform_devices from there. If not, the mpc52xx_declare_of_platform_devices function can directly be used as the init hook. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Paul Mackerras <paulus@samba.org>
255 lines
7.7 KiB
C
255 lines
7.7 KiB
C
/*
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* Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
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* May need to be cleaned as the port goes on ...
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*
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* Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
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* Copyright (C) 2003 MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef __ASM_POWERPC_MPC52xx_H__
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#define __ASM_POWERPC_MPC52xx_H__
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#include <asm/prom.h>
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#endif /* __ASSEMBLY__ */
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/* ======================================================================== */
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/* Structures mapping of some unit register set */
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/* ======================================================================== */
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#ifndef __ASSEMBLY__
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/* Memory Mapping Control */
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struct mpc52xx_mmap_ctl {
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u32 mbar; /* MMAP_CTRL + 0x00 */
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u32 cs0_start; /* MMAP_CTRL + 0x04 */
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u32 cs0_stop; /* MMAP_CTRL + 0x08 */
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u32 cs1_start; /* MMAP_CTRL + 0x0c */
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u32 cs1_stop; /* MMAP_CTRL + 0x10 */
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u32 cs2_start; /* MMAP_CTRL + 0x14 */
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u32 cs2_stop; /* MMAP_CTRL + 0x18 */
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u32 cs3_start; /* MMAP_CTRL + 0x1c */
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u32 cs3_stop; /* MMAP_CTRL + 0x20 */
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u32 cs4_start; /* MMAP_CTRL + 0x24 */
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u32 cs4_stop; /* MMAP_CTRL + 0x28 */
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u32 cs5_start; /* MMAP_CTRL + 0x2c */
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u32 cs5_stop; /* MMAP_CTRL + 0x30 */
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u32 sdram0; /* MMAP_CTRL + 0x34 */
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u32 sdram1; /* MMAP_CTRL + 0X38 */
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u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
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u32 boot_start; /* MMAP_CTRL + 0x4c */
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u32 boot_stop; /* MMAP_CTRL + 0x50 */
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u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
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u32 cs6_start; /* MMAP_CTRL + 0x58 */
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u32 cs6_stop; /* MMAP_CTRL + 0x5c */
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u32 cs7_start; /* MMAP_CTRL + 0x60 */
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u32 cs7_stop; /* MMAP_CTRL + 0x64 */
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};
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/* SDRAM control */
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struct mpc52xx_sdram {
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u32 mode; /* SDRAM + 0x00 */
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u32 ctrl; /* SDRAM + 0x04 */
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u32 config1; /* SDRAM + 0x08 */
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u32 config2; /* SDRAM + 0x0c */
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};
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/* SDMA */
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struct mpc52xx_sdma {
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u32 taskBar; /* SDMA + 0x00 */
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u32 currentPointer; /* SDMA + 0x04 */
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u32 endPointer; /* SDMA + 0x08 */
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u32 variablePointer; /* SDMA + 0x0c */
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u8 IntVect1; /* SDMA + 0x10 */
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u8 IntVect2; /* SDMA + 0x11 */
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u16 PtdCntrl; /* SDMA + 0x12 */
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u32 IntPend; /* SDMA + 0x14 */
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u32 IntMask; /* SDMA + 0x18 */
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u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
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u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
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u32 cReqSelect; /* SDMA + 0x5c */
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u32 task_size0; /* SDMA + 0x60 */
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u32 task_size1; /* SDMA + 0x64 */
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u32 MDEDebug; /* SDMA + 0x68 */
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u32 ADSDebug; /* SDMA + 0x6c */
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u32 Value1; /* SDMA + 0x70 */
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u32 Value2; /* SDMA + 0x74 */
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u32 Control; /* SDMA + 0x78 */
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u32 Status; /* SDMA + 0x7c */
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u32 PTDDebug; /* SDMA + 0x80 */
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};
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/* GPT */
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struct mpc52xx_gpt {
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u32 mode; /* GPTx + 0x00 */
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u32 count; /* GPTx + 0x04 */
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u32 pwm; /* GPTx + 0x08 */
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u32 status; /* GPTx + 0X0c */
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};
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/* GPIO */
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struct mpc52xx_gpio {
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u32 port_config; /* GPIO + 0x00 */
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u32 simple_gpioe; /* GPIO + 0x04 */
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u32 simple_ode; /* GPIO + 0x08 */
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u32 simple_ddr; /* GPIO + 0x0c */
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u32 simple_dvo; /* GPIO + 0x10 */
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u32 simple_ival; /* GPIO + 0x14 */
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u8 outo_gpioe; /* GPIO + 0x18 */
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u8 reserved1[3]; /* GPIO + 0x19 */
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u8 outo_dvo; /* GPIO + 0x1c */
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u8 reserved2[3]; /* GPIO + 0x1d */
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u8 sint_gpioe; /* GPIO + 0x20 */
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u8 reserved3[3]; /* GPIO + 0x21 */
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u8 sint_ode; /* GPIO + 0x24 */
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u8 reserved4[3]; /* GPIO + 0x25 */
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u8 sint_ddr; /* GPIO + 0x28 */
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u8 reserved5[3]; /* GPIO + 0x29 */
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u8 sint_dvo; /* GPIO + 0x2c */
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u8 reserved6[3]; /* GPIO + 0x2d */
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u8 sint_inten; /* GPIO + 0x30 */
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u8 reserved7[3]; /* GPIO + 0x31 */
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u16 sint_itype; /* GPIO + 0x34 */
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u16 reserved8; /* GPIO + 0x36 */
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u8 gpio_control; /* GPIO + 0x38 */
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u8 reserved9[3]; /* GPIO + 0x39 */
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u8 sint_istat; /* GPIO + 0x3c */
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u8 sint_ival; /* GPIO + 0x3d */
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u8 bus_errs; /* GPIO + 0x3e */
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u8 reserved10; /* GPIO + 0x3f */
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};
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#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
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#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
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#define MPC52xx_GPIO_PCI_DIS (1<<15)
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/* GPIO with WakeUp*/
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struct mpc52xx_gpio_wkup {
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u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
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u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
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u8 wkup_ode; /* GPIO_WKUP + 0x04 */
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u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
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u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
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u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
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u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
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u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
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u8 wkup_inten; /* GPIO_WKUP + 0x10 */
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u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
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u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
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u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
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u16 wkup_itype; /* GPIO_WKUP + 0x18 */
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u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
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u8 wkup_maste; /* GPIO_WKUP + 0x1C */
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u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
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u8 wkup_ival; /* GPIO_WKUP + 0x20 */
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u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
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u8 wkup_istat; /* GPIO_WKUP + 0x24 */
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u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
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};
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/* XLB Bus control */
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struct mpc52xx_xlb {
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u8 reserved[0x40];
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u32 config; /* XLB + 0x40 */
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u32 version; /* XLB + 0x44 */
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u32 status; /* XLB + 0x48 */
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u32 int_enable; /* XLB + 0x4c */
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u32 addr_capture; /* XLB + 0x50 */
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u32 bus_sig_capture; /* XLB + 0x54 */
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u32 addr_timeout; /* XLB + 0x58 */
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u32 data_timeout; /* XLB + 0x5c */
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u32 bus_act_timeout; /* XLB + 0x60 */
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u32 master_pri_enable; /* XLB + 0x64 */
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u32 master_priority; /* XLB + 0x68 */
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u32 base_address; /* XLB + 0x6c */
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u32 snoop_window; /* XLB + 0x70 */
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};
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#define MPC52xx_XLB_CFG_PLDIS (1 << 31)
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#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
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/* Clock Distribution control */
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struct mpc52xx_cdm {
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u32 jtag_id; /* CDM + 0x00 reg0 read only */
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u32 rstcfg; /* CDM + 0x04 reg1 read only */
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u32 breadcrumb; /* CDM + 0x08 reg2 */
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u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
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u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
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u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
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u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
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u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
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u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
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u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
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u32 clk_enables; /* CDM + 0x14 reg5 */
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u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
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u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
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u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
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u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
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u8 reserved1; /* CDM + 0x1e reg7 byte2 */
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u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
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u8 soft_reset; /* CDM + 0x20 u8 byte0 */
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u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
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u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
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u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
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u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
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u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
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u8 reserved3; /* CDM + 0x27 reg9 byte3 */
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u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
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u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
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u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
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u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
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u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
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u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
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u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
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u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
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};
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#endif /* __ASSEMBLY__ */
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/* ========================================================================= */
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/* Prototypes for MPC52xx sysdev */
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/* ========================================================================= */
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#ifndef __ASSEMBLY__
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extern void __iomem * mpc52xx_find_and_map(const char *);
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extern unsigned int mpc52xx_find_ipb_freq(struct device_node *node);
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extern void mpc52xx_setup_cpu(void);
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extern void mpc52xx_declare_of_platform_devices(void);
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extern void mpc52xx_init_irq(void);
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extern unsigned int mpc52xx_get_irq(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_POWERPC_MPC52xx_H__ */
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