4c18e77f71
Multiple peripherals in SPEAr share common hardware interrupt lines. This patch adds support for a shared irq layer, which registers hardware irqs by itself and exposes virtual irq numbers to peripherals. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
96 lines
2.7 KiB
C
96 lines
2.7 KiB
C
/*
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* arch/arm/mach-spear3xx/include/mach/spear320.h
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*
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* SPEAr320 Machine specific definition
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifdef CONFIG_MACH_SPEAR320
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#ifndef __MACH_SPEAR320_H
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#define __MACH_SPEAR320_H
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#define SPEAR320_EMI_CTRL_BASE 0x40000000
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#define SPEAR320_EMI_CTRL_SIZE 0x08000000
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#define SPEAR320_FSMC_BASE 0x4C000000
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#define SPEAR320_FSMC_SIZE 0x01000000
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#define SPEAR320_I2S_BASE 0x60000000
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#define SPEAR320_I2S_SIZE 0x10000000
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#define SPEAR320_SDIO_BASE 0x70000000
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#define SPEAR320_SDIO_SIZE 0x10000000
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#define SPEAR320_CLCD_BASE 0x90000000
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#define SPEAR320_CLCD_SIZE 0x10000000
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#define SPEAR320_PAR_PORT_BASE 0xA0000000
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#define SPEAR320_PAR_PORT_SIZE 0x01000000
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#define SPEAR320_CAN0_BASE 0xA1000000
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#define SPEAR320_CAN0_SIZE 0x01000000
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#define SPEAR320_CAN1_BASE 0xA2000000
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#define SPEAR320_CAN1_SIZE 0x01000000
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#define SPEAR320_UART1_BASE 0xA3000000
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#define SPEAR320_UART2_BASE 0xA4000000
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#define SPEAR320_UART_SIZE 0x01000000
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#define SPEAR320_SSP0_BASE 0xA5000000
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#define SPEAR320_SSP0_SIZE 0x01000000
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#define SPEAR320_SSP1_BASE 0xA6000000
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#define SPEAR320_SSP1_SIZE 0x01000000
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#define SPEAR320_I2C_BASE 0xA7000000
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#define SPEAR320_I2C_SIZE 0x01000000
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#define SPEAR320_PWM_BASE 0xA8000000
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#define SPEAR320_PWM_SIZE 0x01000000
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#define SPEAR320_SMII0_BASE 0xAA000000
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#define SPEAR320_SMII0_SIZE 0x01000000
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#define SPEAR320_SMII1_BASE 0xAB000000
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#define SPEAR320_SMII1_SIZE 0x01000000
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#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
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#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
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/* Interrupt registers offsets and masks */
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#define INT_STS_MASK_REG 0x04
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#define INT_CLR_MASK_REG 0x04
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#define INT_ENB_MASK_REG 0x08
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#define GPIO_IRQ_MASK (1 << 0)
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#define I2S_PLAY_IRQ_MASK (1 << 1)
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#define I2S_REC_IRQ_MASK (1 << 2)
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#define EMI_IRQ_MASK (1 << 7)
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#define CLCD_IRQ_MASK (1 << 8)
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#define SPP_IRQ_MASK (1 << 9)
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#define SDIO_IRQ_MASK (1 << 10)
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#define CAN_U_IRQ_MASK (1 << 11)
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#define CAN_L_IRQ_MASK (1 << 12)
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#define UART1_IRQ_MASK (1 << 13)
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#define UART2_IRQ_MASK (1 << 14)
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#define SSP1_IRQ_MASK (1 << 15)
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#define SSP2_IRQ_MASK (1 << 16)
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#define SMII0_IRQ_MASK (1 << 17)
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#define MII1_SMII1_IRQ_MASK (1 << 18)
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#define WAKEUP_SMII0_IRQ_MASK (1 << 19)
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#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
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#define I2C1_IRQ_MASK (1 << 21)
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#define SHIRQ_RAS1_MASK 0x000380
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#define SHIRQ_RAS3_MASK 0x000007
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#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
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#endif /* __MACH_SPEAR320_H */
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#endif /* CONFIG_MACH_SPEAR320 */
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