d6ea3df0d4
Sodaville's SPI controller is very much the same as in PXA25x. The difference: - The RX/TX FIFO is only 4 words deep instead of 16 - No DMA support - The SPI controller offers a CS functionality Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
152 lines
4.5 KiB
C
152 lines
4.5 KiB
C
/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __linux_pxa2xx_spi_h
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#define __linux_pxa2xx_spi_h
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#include <linux/pxa2xx_ssp.h>
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#define PXA2XX_CS_ASSERT (0x01)
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#define PXA2XX_CS_DEASSERT (0x02)
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/* device.platform_data for SSP controller devices */
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struct pxa2xx_spi_master {
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u32 clock_enable;
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u16 num_chipselect;
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u8 enable_dma;
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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*/
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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u8 rx_threshold;
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u8 dma_burst_size;
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u32 timeout;
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u8 enable_loopback;
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int gpio_cs;
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void (*cs_control)(u32 command);
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};
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#ifdef CONFIG_ARCH_PXA
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#include <linux/clk.h>
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#include <mach/dma.h>
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extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
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#else
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/*
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* This is the implemtation for CE4100 on x86. ARM defines them in mach/ or
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* plat/ include path.
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* The CE4100 does not provide DMA support. This bits are here to let the driver
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* compile and will never be used. Maybe we get DMA support at a later point in
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* time.
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*/
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#define DCSR(n) (n)
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#define DSADR(n) (n)
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#define DTADR(n) (n)
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#define DCMD(n) (n)
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#define DRCMR(n) (n)
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#define DCSR_RUN (1 << 31) /* Run Bit */
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#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */
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#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */
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#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
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#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
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#define DCSR_ENDINTR (1 << 2) /* End Interrupt */
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#define DCSR_STARTINTR (1 << 1) /* Start Interrupt */
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#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */
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#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */
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#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
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#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
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#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
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#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
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#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
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#define DCSR_EORINTR (1 << 9) /* The end of Receive */
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#define DRCMR_MAPVLD (1 << 7) /* Map Valid */
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#define DRCMR_CHLNUM 0x1f /* mask for Channel Number */
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#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */
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#define DDADR_STOP (1 << 0) /* Stop */
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#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
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#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
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#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
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#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
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#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
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#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
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#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
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#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
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#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
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#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
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#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
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#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
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#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
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#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
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/*
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* Descriptor structure for PXA's DMA engine
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* Note: this structure must always be aligned to a 16-byte boundary.
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*/
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typedef enum {
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DMA_PRIO_HIGH = 0,
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DMA_PRIO_MEDIUM = 1,
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DMA_PRIO_LOW = 2
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} pxa_dma_prio;
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/*
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* DMA registration
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*/
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static inline int pxa_request_dma(char *name,
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pxa_dma_prio prio,
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void (*irq_handler)(int, void *),
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void *data)
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{
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return -ENODEV;
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}
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static inline void pxa_free_dma(int dma_ch)
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{
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}
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/*
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* The CE4100 does not have the clk framework implemented and SPI clock can
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* not be switched on/off or the divider changed.
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*/
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static inline void clk_disable(struct clk *clk)
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{
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}
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static inline int clk_enable(struct clk *clk)
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{
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return 0;
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}
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static inline unsigned long clk_get_rate(struct clk *clk)
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{
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return 3686400;
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}
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#endif
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#endif
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