18bd057b14
AMD K7/K8 CPUs only save/restore the FOP/FIP/FDP x87 registers in FXSAVE when an exception is pending. This means the value leak through context switches and allow processes to observe some x87 instruction state of other processes. This was actually documented by AMD, but nobody recognized it as being different from Intel before. The fix first adds an optimization: instead of unconditionally calling FNCLEX after each FXSAVE test if ES is pending and skip it when not needed. Then do a x87 load from a kernel variable to clear FOP/FIP/FDP. This means other processes always will only see a constant value defined by the kernel in their FP state. I took some pain to make sure to chose a variable that's already in L1 during context switch to make the overhead of this low. Also alternative() is used to patch away the new code on CPUs who don't need it. Patch for both i386/x86-64. The problem was discovered originally by Jan Beulich. Richard Brunner provided the basic code for the workarounds, with contribution from Jan. This is CVE-2006-1056 Cc: richard.brunner@amd.com Cc: jbeulich@novell.com Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
206 lines
5.7 KiB
C
206 lines
5.7 KiB
C
/*
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* include/asm-x86_64/i387.h
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*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef __ASM_X86_64_I387_H
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#define __ASM_X86_64_I387_H
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/sigcontext.h>
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#include <asm/user.h>
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#include <asm/thread_info.h>
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#include <asm/uaccess.h>
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extern void fpu_init(void);
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extern unsigned int mxcsr_feature_mask;
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extern void mxcsr_feature_mask_init(void);
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extern void init_fpu(struct task_struct *child);
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extern int save_i387(struct _fpstate __user *buf);
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/*
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* FPU lazy state save handling...
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*/
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#define unlazy_fpu(tsk) do { \
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if (task_thread_info(tsk)->status & TS_USEDFPU) \
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save_init_fpu(tsk); \
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} while (0)
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/* Ignore delayed exceptions from user space */
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static inline void tolerant_fwait(void)
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{
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asm volatile("1: fwait\n"
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"2:\n"
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" .section __ex_table,\"a\"\n"
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" .align 8\n"
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" .quad 1b,2b\n"
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" .previous\n");
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}
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#define clear_fpu(tsk) do { \
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if (task_thread_info(tsk)->status & TS_USEDFPU) { \
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tolerant_fwait(); \
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task_thread_info(tsk)->status &= ~TS_USEDFPU; \
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stts(); \
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} \
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} while (0)
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/*
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* ptrace request handers...
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*/
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extern int get_fpregs(struct user_i387_struct __user *buf,
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struct task_struct *tsk);
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extern int set_fpregs(struct task_struct *tsk,
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struct user_i387_struct __user *buf);
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/*
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* i387 state interaction
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*/
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#define get_fpu_mxcsr(t) ((t)->thread.i387.fxsave.mxcsr)
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#define get_fpu_cwd(t) ((t)->thread.i387.fxsave.cwd)
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#define get_fpu_fxsr_twd(t) ((t)->thread.i387.fxsave.twd)
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#define get_fpu_swd(t) ((t)->thread.i387.fxsave.swd)
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#define set_fpu_cwd(t,val) ((t)->thread.i387.fxsave.cwd = (val))
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#define set_fpu_swd(t,val) ((t)->thread.i387.fxsave.swd = (val))
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#define set_fpu_fxsr_twd(t,val) ((t)->thread.i387.fxsave.twd = (val))
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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/* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. The kernel data segment can be sometimes 0 and sometimes
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new user value. Both should be ok.
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Use the PDA as safe address because it should be already in L1. */
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static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
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{
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if (unlikely(fx->swd & X87_FSW_ES))
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asm volatile("fnclex");
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alternative_input(ASM_NOP8 ASM_NOP2,
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" emms\n" /* clear stack tags */
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" fildl %%gs:0", /* load to clear state */
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X86_FEATURE_FXSAVE_LEAK);
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}
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static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
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{
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int err;
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asm volatile("1: rex64/fxrstor (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 8\n"
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" .quad 1b,3b\n"
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".previous"
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: [err] "=r" (err)
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#if 0 /* See comment in __fxsave_clear() below. */
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: [fx] "r" (fx), "m" (*fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
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#endif
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if (unlikely(err))
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init_fpu(current);
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return err;
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}
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static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
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{
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int err;
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asm volatile("1: rex64/fxsave (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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".section __ex_table,\"a\"\n"
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" .align 8\n"
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" .quad 1b,3b\n"
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".previous"
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: [err] "=r" (err), "=m" (*fx)
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#if 0 /* See comment in __fxsave_clear() below. */
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: [fx] "r" (fx), "0" (0));
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#else
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: [fx] "cdaSDb" (fx), "0" (0));
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#endif
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if (unlikely(err))
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__clear_user(fx, sizeof(struct i387_fxsave_struct));
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/* No need to clear here because the caller clears USED_MATH */
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return err;
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}
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static inline void __fxsave_clear(struct task_struct *tsk)
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{
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/* Using "rex64; fxsave %0" is broken because, if the memory operand
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uses any extended registers for addressing, a second REX prefix
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will be generated (to the assembler, rex64 followed by semicolon
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is a separate instruction), and hence the 64-bitness is lost. */
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#if 0
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/* Using "fxsaveq %0" would be the ideal choice, but is only supported
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starting with gas 2.16. */
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__asm__ __volatile__("fxsaveq %0"
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: "=m" (tsk->thread.i387.fxsave));
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#elif 0
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/* Using, as a workaround, the properly prefixed form below isn't
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accepted by any binutils version so far released, complaining that
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the same type of prefix is used twice if an extended register is
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needed for addressing (fix submitted to mainline 2005-11-21). */
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__asm__ __volatile__("rex64/fxsave %0"
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: "=m" (tsk->thread.i387.fxsave));
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#else
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/* This, however, we can work around by forcing the compiler to select
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an addressing mode that doesn't require extended registers. */
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__asm__ __volatile__("rex64/fxsave %P2(%1)"
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: "=m" (tsk->thread.i387.fxsave)
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: "cdaSDb" (tsk),
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"i" (offsetof(__typeof__(*tsk),
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thread.i387.fxsave)));
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#endif
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clear_fpu_state(&tsk->thread.i387.fxsave);
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}
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static inline void kernel_fpu_begin(void)
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{
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struct thread_info *me = current_thread_info();
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preempt_disable();
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if (me->status & TS_USEDFPU) {
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__fxsave_clear(me->task);
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me->status &= ~TS_USEDFPU;
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return;
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}
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clts();
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}
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static inline void kernel_fpu_end(void)
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{
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stts();
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preempt_enable();
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}
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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__fxsave_clear(tsk);
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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stts();
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}
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/*
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* This restores directly out of user space. Exceptions are handled.
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*/
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static inline int restore_i387(struct _fpstate __user *buf)
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{
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return restore_fpu_checking((__force struct i387_fxsave_struct *)buf);
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}
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#endif /* __ASM_X86_64_I387_H */
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