ffadcc2ff4
When changing power states from D0->DX and then from DX->D0, some Intel PCIE chipsets will cause a device reset to occur. This will cause problems for any D State other than D3, since any state information that the driver will expect to be present coming from a D1 or D2 state will have been cleared. This patch addes a flag to the pci_dev structure to indicate that devices should not use states D1 or D2, and will set that flag for the affected chipsets. This patch also modifies pci_set_power_state() so that when a device driver tries to set the power state on a device that is downstream from an affected chipset, or on one of the affected devices it only allows state changes to or from D0 & D3. In addition, this patch allows the delay time between D3->D0 to be changed via a quirk. These chipsets also need additional time to change states beyond the normal 10ms. Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
101 lines
4.1 KiB
C
101 lines
4.1 KiB
C
/* Functions internal to the PCI core code */
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extern int pci_uevent(struct device *dev, char **envp, int num_envp,
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char *buffer, int buffer_size);
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extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
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extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
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extern void pci_cleanup_rom(struct pci_dev *dev);
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extern int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
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resource_size_t size, resource_size_t align,
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resource_size_t min, unsigned int type_mask,
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void (*alignf)(void *, struct resource *,
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resource_size_t, resource_size_t),
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void *alignf_data);
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/* Firmware callbacks */
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extern int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
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extern int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t state);
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extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
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extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
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extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
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extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
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extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
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extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
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/* PCI /proc functions */
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#ifdef CONFIG_PROC_FS
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extern int pci_proc_attach_device(struct pci_dev *dev);
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extern int pci_proc_detach_device(struct pci_dev *dev);
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extern int pci_proc_detach_bus(struct pci_bus *bus);
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#else
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static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
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#endif
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/* Functions for PCI Hotplug drivers to use */
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extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
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extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
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extern void pci_remove_legacy_files(struct pci_bus *bus);
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/* Lock for read/write access to pci device and bus lists */
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extern struct rw_semaphore pci_bus_sem;
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#ifdef CONFIG_X86_IO_APIC
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extern int pci_msi_quirk;
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#else
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#define pci_msi_quirk 0
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#endif
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extern unsigned int pci_pm_d3_delay;
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#ifdef CONFIG_PCI_MSI
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void disable_msi_mode(struct pci_dev *dev, int pos, int type);
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void pci_no_msi(void);
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#else
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static inline void disable_msi_mode(struct pci_dev *dev, int pos, int type) { }
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static inline void pci_no_msi(void) { }
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#endif
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#if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM)
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int pci_save_msi_state(struct pci_dev *dev);
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int pci_save_msix_state(struct pci_dev *dev);
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void pci_restore_msi_state(struct pci_dev *dev);
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void pci_restore_msix_state(struct pci_dev *dev);
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#else
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static inline int pci_save_msi_state(struct pci_dev *dev) { return 0; }
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static inline int pci_save_msix_state(struct pci_dev *dev) { return 0; }
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static inline void pci_restore_msi_state(struct pci_dev *dev) {}
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static inline void pci_restore_msix_state(struct pci_dev *dev) {}
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#endif
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static inline int pci_no_d1d2(struct pci_dev *dev)
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{
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unsigned int parent_dstates = 0;
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if (dev->bus->self)
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parent_dstates = dev->bus->self->no_d1d2;
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return (dev->no_d1d2 || parent_dstates);
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}
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extern int pcie_mch_quirk;
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extern struct device_attribute pci_dev_attrs[];
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extern struct class_device_attribute class_device_attr_cpuaffinity;
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/**
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* pci_match_one_device - Tell if a PCI device structure has a matching
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* PCI device id structure
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* @id: single PCI device id structure to match
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* @dev: the PCI device structure to match against
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*
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* Returns the matching pci_device_id structure or %NULL if there is no match.
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*/
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static inline const struct pci_device_id *
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pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
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{
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if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
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(id->device == PCI_ANY_ID || id->device == dev->device) &&
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(id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
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(id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
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!((id->class ^ dev->class) & id->class_mask))
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return id;
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return NULL;
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}
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