94dee171df
> #define hw_interrupt_type irq_chip > typedef struct irq_chip hw_irq_controller; > #define no_irq_type no_irq_chip > typedef struct irq_desc irq_desc_t; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
162 lines
3.9 KiB
C
162 lines
3.9 KiB
C
/*
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* Copyright 2002 Momentum Computer
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* Author: mdharm@momenco.com
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* Copyright (C) 2004 Ralf Baechle <ralf@linux-mips.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/kernel_stat.h>
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#include <linux/mv643xx.h>
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#include <linux/sched.h>
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#include <asm/ptrace.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/marvell.h>
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static unsigned int irq_base;
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static inline int ls1bit32(unsigned int x)
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{
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int b = 31, s;
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s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
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s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
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s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
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s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
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s = 1; if (x << 1 == 0) s = 0; b -= s;
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return b;
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}
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/* mask off an interrupt -- 1 is enable, 0 is disable */
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static inline void mask_mv64340_irq(unsigned int irq)
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{
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uint32_t value;
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if (irq < (irq_base + 32)) {
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value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
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value &= ~(1 << (irq - irq_base));
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MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
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} else {
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value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
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value &= ~(1 << (irq - irq_base - 32));
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MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
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}
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}
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/* unmask an interrupt -- 1 is enable, 0 is disable */
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static inline void unmask_mv64340_irq(unsigned int irq)
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{
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uint32_t value;
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if (irq < (irq_base + 32)) {
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value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
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value |= 1 << (irq - irq_base);
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MV_WRITE(MV64340_INTERRUPT0_MASK_0_LOW, value);
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} else {
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value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
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value |= 1 << (irq - irq_base - 32);
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MV_WRITE(MV64340_INTERRUPT0_MASK_0_HIGH, value);
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}
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}
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/*
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* Enables the IRQ on Marvell Chip
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*/
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static void enable_mv64340_irq(unsigned int irq)
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{
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unmask_mv64340_irq(irq);
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}
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/*
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* Initialize the IRQ on Marvell Chip
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*/
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static unsigned int startup_mv64340_irq(unsigned int irq)
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{
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unmask_mv64340_irq(irq);
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return 0;
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}
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/*
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* Disables the IRQ on Marvell Chip
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*/
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static void disable_mv64340_irq(unsigned int irq)
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{
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mask_mv64340_irq(irq);
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}
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/*
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* Masks and ACKs an IRQ
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*/
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static void mask_and_ack_mv64340_irq(unsigned int irq)
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{
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mask_mv64340_irq(irq);
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}
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/*
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* End IRQ processing
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*/
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static void end_mv64340_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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unmask_mv64340_irq(irq);
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}
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/*
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* Interrupt handler for interrupts coming from the Marvell chip.
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* It could be built in ethernet ports etc...
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*/
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void ll_mv64340_irq(struct pt_regs *regs)
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{
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unsigned int irq_src_low, irq_src_high;
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unsigned int irq_mask_low, irq_mask_high;
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/* read the interrupt status registers */
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irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
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irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
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irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
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irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
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/* mask for just the interrupts we want */
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irq_src_low &= irq_mask_low;
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irq_src_high &= irq_mask_high;
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if (irq_src_low)
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do_IRQ(ls1bit32(irq_src_low) + irq_base, regs);
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else
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do_IRQ(ls1bit32(irq_src_high) + irq_base + 32, regs);
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}
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#define shutdown_mv64340_irq disable_mv64340_irq
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struct irq_chip mv64340_irq_type = {
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.typename = "MV-64340",
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.startup = startup_mv64340_irq,
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.shutdown = shutdown_mv64340_irq,
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.enable = enable_mv64340_irq,
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.disable = disable_mv64340_irq,
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.ack = mask_and_ack_mv64340_irq,
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.end = end_mv64340_irq,
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};
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void __init mv64340_irq_init(unsigned int base)
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{
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int i;
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/* Reset irq handlers pointers to NULL */
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for (i = base; i < base + 64; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 2;
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irq_desc[i].chip = &mv64340_irq_type;
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}
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irq_base = base;
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}
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