cb7a01ac32
Move ancillary I2C drivers into drivers/media/i2c, in order to better organize them. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
245 lines
8.2 KiB
C
245 lines
8.2 KiB
C
/*
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* saa7191.h - Philips SAA7191 video decoder driver
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*
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* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
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* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _SAA7191_H_
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#define _SAA7191_H_
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/* Philips SAA7191 DMSD I2C bus address */
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#define SAA7191_ADDR 0x8a
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/* Register subaddresses. */
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#define SAA7191_REG_IDEL 0x00
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#define SAA7191_REG_HSYB 0x01
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#define SAA7191_REG_HSYS 0x02
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#define SAA7191_REG_HCLB 0x03
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#define SAA7191_REG_HCLS 0x04
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#define SAA7191_REG_HPHI 0x05
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#define SAA7191_REG_LUMA 0x06
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#define SAA7191_REG_HUEC 0x07
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#define SAA7191_REG_CKTQ 0x08 /* bits 3-7 */
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#define SAA7191_REG_CKTS 0x09 /* bits 3-7 */
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#define SAA7191_REG_PLSE 0x0a
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#define SAA7191_REG_SESE 0x0b
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#define SAA7191_REG_GAIN 0x0c
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#define SAA7191_REG_STDC 0x0d
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#define SAA7191_REG_IOCK 0x0e
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#define SAA7191_REG_CTL3 0x0f
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#define SAA7191_REG_CTL4 0x10
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#define SAA7191_REG_CHCV 0x11
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#define SAA7191_REG_HS6B 0x14
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#define SAA7191_REG_HS6S 0x15
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#define SAA7191_REG_HC6B 0x16
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#define SAA7191_REG_HC6S 0x17
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#define SAA7191_REG_HP6I 0x18
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#define SAA7191_REG_STATUS 0xff /* not really a subaddress */
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/* Status Register definitions */
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#define SAA7191_STATUS_CODE 0x01 /* color detected flag */
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#define SAA7191_STATUS_FIDT 0x20 /* signal type 50/60 Hz */
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#define SAA7191_STATUS_HLCK 0x40 /* PLL unlocked(1)/locked(0) */
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#define SAA7191_STATUS_STTC 0x80 /* tv/vtr time constant */
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/* Luminance Control Register definitions */
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/* input mode select bit:
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* 0=CVBS (chrominance trap active), 1=S-Video (trap bypassed) */
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#define SAA7191_LUMA_BYPS 0x80
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/* pre-filter (only when chrominance trap is active) */
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#define SAA7191_LUMA_PREF 0x40
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/* aperture bandpass to select different characteristics with maximums
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* (bits 4-5) */
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#define SAA7191_LUMA_BPSS_MASK 0x30
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#define SAA7191_LUMA_BPSS_SHIFT 4
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#define SAA7191_LUMA_BPSS_3 0x30
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#define SAA7191_LUMA_BPSS_2 0x20
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#define SAA7191_LUMA_BPSS_1 0x10
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#define SAA7191_LUMA_BPSS_0 0x00
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/* coring range for high frequency components according to 8-bit luminance
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* (bits 2-3)
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* 0=coring off, n= (+-)n LSB */
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#define SAA7191_LUMA_CORI_MASK 0x0c
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#define SAA7191_LUMA_CORI_SHIFT 2
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#define SAA7191_LUMA_CORI_3 0x0c
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#define SAA7191_LUMA_CORI_2 0x08
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#define SAA7191_LUMA_CORI_1 0x04
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#define SAA7191_LUMA_CORI_0 0x00
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/* aperture bandpass filter weights high frequency components of luminance
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* signal (bits 0-1)
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* 0=factor 0, 1=0.25, 2=0.5, 3=1 */
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#define SAA7191_LUMA_APER_MASK 0x03
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#define SAA7191_LUMA_APER_SHIFT 0
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#define SAA7191_LUMA_APER_3 0x03
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#define SAA7191_LUMA_APER_2 0x02
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#define SAA7191_LUMA_APER_1 0x01
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#define SAA7191_LUMA_APER_0 0x00
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/* Chrominance Gain Control Settings Register definitions */
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/* colour on: 0=automatic colour-killer enabled, 1=forced colour on */
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#define SAA7191_GAIN_COLO 0x80
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/* chrominance gain control (AGC filter)
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* 0=loop filter time constant slow, 1=medium, 2=fast, 3=actual gain */
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#define SAA7191_GAIN_LFIS_MASK 0x60
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#define SAA7191_GAIN_LFIS_SHIFT 5
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#define SAA7191_GAIN_LFIS_3 0x60
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#define SAA7191_GAIN_LFIS_2 0x40
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#define SAA7191_GAIN_LFIS_1 0x20
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#define SAA7191_GAIN_LFIS_0 0x00
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/* Standard/Mode Control Register definitions */
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/* tv/vtr mode bit: 0=TV mode (slow time constant),
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* 1=VTR mode (fast time constant) */
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#define SAA7191_STDC_VTRC 0x80
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/* SAA7191B-specific functions enable (RTCO, ODD and GPSW0 outputs)
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* 0=outputs set to high-impedance (circuit equals SAA7191), 1=enabled */
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#define SAA7191_STDC_NFEN 0x08
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/* HREF generation: 0=like SAA7191, 1=HREF is 8xLLC2 clocks earlier */
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#define SAA7191_STDC_HRMV 0x04
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/* general purpose switch 0
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* (not used with VINO afaik) */
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#define SAA7191_STDC_GPSW0 0x02
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/* SECAM mode bit: 0=other standards, 1=SECAM */
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#define SAA7191_STDC_SECS 0x01
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/* I/O and Clock Control Register definitions */
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/* horizontal clock PLL: 0=PLL closed,
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* 1=PLL circuit open and horizontal freq fixed */
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#define SAA7191_IOCK_HPLL 0x80
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/* colour-difference output enable (outputs UV0-UV7) */
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#define SAA7191_IOCK_OEDC 0x40
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/* H-sync output enable */
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#define SAA7191_IOCK_OEHS 0x20
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/* V-sync output enable */
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#define SAA7191_IOCK_OEVS 0x10
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/* luminance output enable (outputs Y0-Y7) */
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#define SAA7191_IOCK_OEDY 0x08
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/* S-VHS bit (chrominance from CVBS or from chrominance input):
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* 0=controlled by BYPS-bit, 1=from chrominance input */
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#define SAA7191_IOCK_CHRS 0x04
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/* general purpose switch 2
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* VINO-specific: 0=used with CVBS, 1=used with S-Video */
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#define SAA7191_IOCK_GPSW2 0x02
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/* general purpose switch 1 */
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/* VINO-specific: 0=always, 1=not used!*/
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#define SAA7191_IOCK_GPSW1 0x01
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/* Miscellaneous Control #1 Register definitions */
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/* automatic field detection (50/60Hz standard) */
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#define SAA7191_CTL3_AUFD 0x80
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/* field select: (if AUFD=0)
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* 0=50Hz (625 lines), 1=60Hz (525 lines) */
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#define SAA7191_CTL3_FSEL 0x40
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/* SECAM cross-colour reduction enable */
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#define SAA7191_CTL3_SXCR 0x20
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/* sync and clamping pulse enable (HCL and HSY outputs) */
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#define SAA7191_CTL3_SCEN 0x10
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/* output format: 0=4:1:1, 1=4:2:2 (4:2:2 for VINO) */
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#define SAA7191_CTL3_OFTS 0x08
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/* luminance delay compensation
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* 0=0*2/LLC, 1=+1*2/LLC, 2=+2*2/LLC, 3=+3*2/LLC,
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* 4=-4*2/LLC, 5=-3*2/LLC, 6=-2*2/LLC, 7=-1*2/LLC
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* step size = 2/LLC = 67.8ns for 50Hz, 81.5ns for 60Hz */
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#define SAA7191_CTL3_YDEL_MASK 0x07
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#define SAA7191_CTL3_YDEL_SHIFT 0
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#define SAA7191_CTL3_YDEL2 0x04
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#define SAA7191_CTL3_YDEL1 0x02
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#define SAA7191_CTL3_YDEL0 0x01
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/* Miscellaneous Control #2 Register definitions */
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/* select HREF position
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* 0=normal, HREF is matched to YUV output port,
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* 1=HREF is matched to CVBS input port */
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#define SAA7191_CTL4_HRFS 0x04
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/* vertical noise reduction
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* 0=normal, 1=searching window, 2=auto-deflection, 3=reduction bypassed */
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#define SAA7191_CTL4_VNOI_MASK 0x03
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#define SAA7191_CTL4_VNOI_SHIFT 0
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#define SAA7191_CTL4_VNOI_3 0x03
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#define SAA7191_CTL4_VNOI_2 0x02
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#define SAA7191_CTL4_VNOI_1 0x01
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#define SAA7191_CTL4_VNOI_0 0x00
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/* Chrominance Gain Control Register definitions
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* - for QAM-modulated input signals, effects output amplitude
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* (SECAM gain fixed)
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* (nominal values for UV CCIR level) */
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#define SAA7191_CHCV_NTSC 0x2c
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#define SAA7191_CHCV_PAL 0x59
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/* Driver interface definitions */
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#define SAA7191_INPUT_COMPOSITE 0
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#define SAA7191_INPUT_SVIDEO 1
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#define SAA7191_NORM_PAL 1
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#define SAA7191_NORM_NTSC 2
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#define SAA7191_NORM_SECAM 3
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struct saa7191_status {
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/* 0=no signal, 1=signal detected */
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int signal;
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/* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
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int signal_60hz;
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/* 0=no color detected, 1=color detected */
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int color;
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/* current SAA7191_INPUT_ */
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int input;
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/* current SAA7191_NORM_ */
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int norm;
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};
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#define SAA7191_BANDPASS_MIN 0x00
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#define SAA7191_BANDPASS_MAX 0x03
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#define SAA7191_BANDPASS_DEFAULT 0x00
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#define SAA7191_BANDPASS_WEIGHT_MIN 0x00
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#define SAA7191_BANDPASS_WEIGHT_MAX 0x03
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#define SAA7191_BANDPASS_WEIGHT_DEFAULT 0x01
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#define SAA7191_CORING_MIN 0x00
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#define SAA7191_CORING_MAX 0x03
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#define SAA7191_CORING_DEFAULT 0x00
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#define SAA7191_HUE_MIN 0x00
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#define SAA7191_HUE_MAX 0xff
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#define SAA7191_HUE_DEFAULT 0x80
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#define SAA7191_VTRC_MIN 0x00
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#define SAA7191_VTRC_MAX 0x01
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#define SAA7191_VTRC_DEFAULT 0x00
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#define SAA7191_FORCE_COLOUR_MIN 0x00
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#define SAA7191_FORCE_COLOUR_MAX 0x01
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#define SAA7191_FORCE_COLOUR_DEFAULT 0x00
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#define SAA7191_CHROMA_GAIN_MIN 0x00
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#define SAA7191_CHROMA_GAIN_MAX 0x03
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#define SAA7191_CHROMA_GAIN_DEFAULT 0x00
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#define SAA7191_LUMA_DELAY_MIN -0x04
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#define SAA7191_LUMA_DELAY_MAX 0x03
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#define SAA7191_LUMA_DELAY_DEFAULT 0x01
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#define SAA7191_VNR_MIN 0x00
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#define SAA7191_VNR_MAX 0x03
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#define SAA7191_VNR_DEFAULT 0x00
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#define SAA7191_CONTROL_BANDPASS (V4L2_CID_PRIVATE_BASE + 0)
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#define SAA7191_CONTROL_BANDPASS_WEIGHT (V4L2_CID_PRIVATE_BASE + 1)
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#define SAA7191_CONTROL_CORING (V4L2_CID_PRIVATE_BASE + 2)
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#define SAA7191_CONTROL_FORCE_COLOUR (V4L2_CID_PRIVATE_BASE + 3)
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#define SAA7191_CONTROL_CHROMA_GAIN (V4L2_CID_PRIVATE_BASE + 4)
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#define SAA7191_CONTROL_VTRC (V4L2_CID_PRIVATE_BASE + 5)
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#define SAA7191_CONTROL_LUMA_DELAY (V4L2_CID_PRIVATE_BASE + 6)
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#define SAA7191_CONTROL_VNR (V4L2_CID_PRIVATE_BASE + 7)
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#define DECODER_SAA7191_GET_STATUS _IOR('d', 195, struct saa7191_status)
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#define DECODER_SAA7191_SET_NORM _IOW('d', 196, int)
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#endif
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