1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
615 lines
26 KiB
C
615 lines
26 KiB
C
/*
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* hp100.h: Hewlett Packard HP10/100VG ANY LAN ethernet driver for Linux.
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*
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* $Id: hp100.h,v 1.51 1997/04/08 14:26:42 floeff Exp floeff $
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*
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* Authors: Jaroslav Kysela, <perex@pf.jcu.cz>
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* Siegfried Loeffler <floeff@tunix.mathematik.uni-stuttgart.de>
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*
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* This driver is based on the 'hpfepkt' crynwr packet driver.
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*
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* This source/code is public free; you can distribute it and/or modify
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* it under terms of the GNU General Public License (published by the
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* Free Software Foundation) either version two of this License, or any
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* later version.
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*/
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/****************************************************************************
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* Hardware Constants
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****************************************************************************/
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/*
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* Page Identifiers
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* (Swap Paging Register, PAGING, bits 3:0, Offset 0x02)
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*/
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#define HP100_PAGE_PERFORMANCE 0x0 /* Page 0 */
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#define HP100_PAGE_MAC_ADDRESS 0x1 /* Page 1 */
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#define HP100_PAGE_HW_MAP 0x2 /* Page 2 */
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#define HP100_PAGE_EEPROM_CTRL 0x3 /* Page 3 */
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#define HP100_PAGE_MAC_CTRL 0x4 /* Page 4 */
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#define HP100_PAGE_MMU_CFG 0x5 /* Page 5 */
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#define HP100_PAGE_ID_MAC_ADDR 0x6 /* Page 6 */
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#define HP100_PAGE_MMU_POINTER 0x7 /* Page 7 */
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/* Registers that are present on all pages */
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#define HP100_REG_HW_ID 0x00 /* R: (16) Unique card ID */
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#define HP100_REG_TRACE 0x00 /* W: (16) Used for debug output */
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#define HP100_REG_PAGING 0x02 /* R: (16),15:4 Card ID */
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/* W: (16),3:0 Switch pages */
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#define HP100_REG_OPTION_LSW 0x04 /* RW: (16) Select card functions */
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#define HP100_REG_OPTION_MSW 0x06 /* RW: (16) Select card functions */
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/* Page 0 - Performance */
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#define HP100_REG_IRQ_STATUS 0x08 /* RW: (16) Which ints are pending */
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#define HP100_REG_IRQ_MASK 0x0a /* RW: (16) Select ints to allow */
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#define HP100_REG_FRAGMENT_LEN 0x0c /* W: (16)12:0 Current fragment len */
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/* Note: For 32 bit systems, fragment len and offset registers are available */
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/* at offset 0x28 and 0x2c, where they can be written as 32bit values. */
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#define HP100_REG_OFFSET 0x0e /* RW: (16)12:0 Offset to start read */
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#define HP100_REG_DATA32 0x10 /* RW: (32) I/O mode data port */
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#define HP100_REG_DATA16 0x12 /* RW: WORDs must be read from here */
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#define HP100_REG_TX_MEM_FREE 0x14 /* RD: (32) Amount of free Tx mem */
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#define HP100_REG_TX_PDA_L 0x14 /* W: (32) BM: Ptr to PDL, Low Pri */
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#define HP100_REG_TX_PDA_H 0x1c /* W: (32) BM: Ptr to PDL, High Pri */
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#define HP100_REG_RX_PKT_CNT 0x18 /* RD: (8) Rx count of pkts on card */
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#define HP100_REG_TX_PKT_CNT 0x19 /* RD: (8) Tx count of pkts on card */
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#define HP100_REG_RX_PDL 0x1a /* R: (8) BM: # rx pdl not executed */
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#define HP100_REG_TX_PDL 0x1b /* R: (8) BM: # tx pdl not executed */
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#define HP100_REG_RX_PDA 0x18 /* W: (32) BM: Up to 31 addresses */
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/* which point to a PDL */
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#define HP100_REG_SL_EARLY 0x1c /* (32) Enhanced Slave Early Rx */
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#define HP100_REG_STAT_DROPPED 0x20 /* R (12) Dropped Packet Counter */
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#define HP100_REG_STAT_ERRORED 0x22 /* R (8) Errored Packet Counter */
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#define HP100_REG_STAT_ABORT 0x23 /* R (8) Abort Counter/OW Coll. Flag */
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#define HP100_REG_RX_RING 0x24 /* W (32) Slave: RX Ring Pointers */
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#define HP100_REG_32_FRAGMENT_LEN 0x28 /* W (13) Slave: Fragment Length Reg */
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#define HP100_REG_32_OFFSET 0x2c /* W (16) Slave: Offset Register */
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/* Page 1 - MAC Address/Hash Table */
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#define HP100_REG_MAC_ADDR 0x08 /* RW: (8) Cards MAC address */
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#define HP100_REG_HASH_BYTE0 0x10 /* RW: (8) Cards multicast filter */
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/* Page 2 - Hardware Mapping */
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#define HP100_REG_MEM_MAP_LSW 0x08 /* RW: (16) LSW of cards mem addr */
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#define HP100_REG_MEM_MAP_MSW 0x0a /* RW: (16) MSW of cards mem addr */
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#define HP100_REG_IO_MAP 0x0c /* RW: (8) Cards I/O address */
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#define HP100_REG_IRQ_CHANNEL 0x0d /* RW: (8) IRQ and edge/level int */
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#define HP100_REG_SRAM 0x0e /* RW: (8) How much RAM on card */
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#define HP100_REG_BM 0x0f /* RW: (8) Controls BM functions */
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/* New on Page 2 for ETR chips: */
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#define HP100_REG_MODECTRL1 0x10 /* RW: (8) Mode Control 1 */
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#define HP100_REG_MODECTRL2 0x11 /* RW: (8) Mode Control 2 */
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#define HP100_REG_PCICTRL1 0x12 /* RW: (8) PCI Cfg 1 */
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#define HP100_REG_PCICTRL2 0x13 /* RW: (8) PCI Cfg 2 */
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#define HP100_REG_PCIBUSMLAT 0x15 /* RW: (8) PCI Bus Master Latency */
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#define HP100_REG_EARLYTXCFG 0x16 /* RW: (16) Early TX Cfg/Cntrl Reg */
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#define HP100_REG_EARLYRXCFG 0x18 /* RW: (8) Early RX Cfg/Cntrl Reg */
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#define HP100_REG_ISAPNPCFG1 0x1a /* RW: (8) ISA PnP Cfg/Cntrl Reg 1 */
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#define HP100_REG_ISAPNPCFG2 0x1b /* RW: (8) ISA PnP Cfg/Cntrl Reg 2 */
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/* Page 3 - EEPROM/Boot ROM */
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#define HP100_REG_EEPROM_CTRL 0x08 /* RW: (16) Used to load EEPROM */
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#define HP100_REG_BOOTROM_CTRL 0x0a
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/* Page 4 - LAN Configuration (MAC_CTRL) */
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#define HP100_REG_10_LAN_CFG_1 0x08 /* RW: (8) Set 10M XCVR functions */
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#define HP100_REG_10_LAN_CFG_2 0x09 /* RW: (8) 10M XCVR functions */
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#define HP100_REG_VG_LAN_CFG_1 0x0a /* RW: (8) Set 100M XCVR functions */
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#define HP100_REG_VG_LAN_CFG_2 0x0b /* RW: (8) 100M LAN Training cfgregs */
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#define HP100_REG_MAC_CFG_1 0x0c /* RW: (8) Types of pkts to accept */
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#define HP100_REG_MAC_CFG_2 0x0d /* RW: (8) Misc MAC functions */
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#define HP100_REG_MAC_CFG_3 0x0e /* RW: (8) Misc MAC functions */
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#define HP100_REG_MAC_CFG_4 0x0f /* R: (8) Misc MAC states */
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#define HP100_REG_DROPPED 0x10 /* R: (16),11:0 Pkts cant fit in mem */
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#define HP100_REG_CRC 0x12 /* R: (8) Pkts with CRC */
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#define HP100_REG_ABORT 0x13 /* R: (8) Aborted Tx pkts */
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#define HP100_REG_TRAIN_REQUEST 0x14 /* RW: (16) Endnode MAC register. */
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#define HP100_REG_TRAIN_ALLOW 0x16 /* R: (16) Hub allowed register */
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/* Page 5 - MMU */
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#define HP100_REG_RX_MEM_STOP 0x0c /* RW: (16) End of Rx ring addr */
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#define HP100_REG_TX_MEM_STOP 0x0e /* RW: (16) End of Tx ring addr */
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#define HP100_REG_PDL_MEM_STOP 0x10 /* Not used by 802.12 devices */
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#define HP100_REG_ECB_MEM_STOP 0x14 /* I've no idea what this is */
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/* Page 6 - Card ID/Physical LAN Address */
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#define HP100_REG_BOARD_ID 0x08 /* R: (8) EISA/ISA card ID */
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#define HP100_REG_BOARD_IO_CHCK 0x0c /* R: (8) Added to ID to get FFh */
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#define HP100_REG_SOFT_MODEL 0x0d /* R: (8) Config program defined */
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#define HP100_REG_LAN_ADDR 0x10 /* R: (8) MAC addr of card */
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#define HP100_REG_LAN_ADDR_CHCK 0x16 /* R: (8) Added to addr to get FFh */
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/* Page 7 - MMU Current Pointers */
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#define HP100_REG_PTR_RXSTART 0x08 /* R: (16) Current begin of Rx ring */
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#define HP100_REG_PTR_RXEND 0x0a /* R: (16) Current end of Rx ring */
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#define HP100_REG_PTR_TXSTART 0x0c /* R: (16) Current begin of Tx ring */
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#define HP100_REG_PTR_TXEND 0x0e /* R: (16) Current end of Rx ring */
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#define HP100_REG_PTR_RPDLSTART 0x10
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#define HP100_REG_PTR_RPDLEND 0x12
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#define HP100_REG_PTR_RINGPTRS 0x14
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#define HP100_REG_PTR_MEMDEBUG 0x1a
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/* ------------------------------------------------------------------------ */
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/*
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* Hardware ID Register I (Always available, HW_ID, Offset 0x00)
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*/
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#define HP100_HW_ID_CASCADE 0x4850 /* Identifies Cascade Chip */
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/*
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* Hardware ID Register 2 & Paging Register
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* (Always available, PAGING, Offset 0x02)
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* Bits 15:4 are for the Chip ID
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*/
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#define HP100_CHIPID_MASK 0xFFF0
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#define HP100_CHIPID_SHASTA 0x5350 /* Not 802.12 compliant */
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/* EISA BM/SL, MCA16/32 SL, ISA SL */
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#define HP100_CHIPID_RAINIER 0x5360 /* Not 802.12 compliant EISA BM, */
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/* PCI SL, MCA16/32 SL, ISA SL */
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#define HP100_CHIPID_LASSEN 0x5370 /* 802.12 compliant PCI BM, PCI SL */
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/* LRF supported */
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/*
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* Option Registers I and II
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* (Always available, OPTION_LSW, Offset 0x04-0x05)
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*/
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#define HP100_DEBUG_EN 0x8000 /* 0:Dis., 1:Enable Debug Dump Ptr. */
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#define HP100_RX_HDR 0x4000 /* 0:Dis., 1:Enable putting pkt into */
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/* system mem. before Rx interrupt */
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#define HP100_MMAP_DIS 0x2000 /* 0:Enable, 1:Disable mem.mapping. */
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/* MMAP_DIS must be 0 and MEM_EN */
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/* must be 1 for memory-mapped */
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/* mode to be enabled */
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#define HP100_EE_EN 0x1000 /* 0:Disable,1:Enable EEPROM writing */
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#define HP100_BM_WRITE 0x0800 /* 0:Slave, 1:Bus Master for Tx data */
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#define HP100_BM_READ 0x0400 /* 0:Slave, 1:Bus Master for Rx data */
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#define HP100_TRI_INT 0x0200 /* 0:Don't, 1:Do tri-state the int */
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#define HP100_MEM_EN 0x0040 /* Config program set this to */
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/* 0:Disable, 1:Enable mem map. */
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/* See MMAP_DIS. */
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#define HP100_IO_EN 0x0020 /* 1:Enable I/O transfers */
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#define HP100_BOOT_EN 0x0010 /* 1:Enable boot ROM access */
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#define HP100_FAKE_INT 0x0008 /* 1:int */
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#define HP100_INT_EN 0x0004 /* 1:Enable ints from card */
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#define HP100_HW_RST 0x0002 /* 0:Reset, 1:Out of reset */
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/* NIC reset on 0 to 1 transition */
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/*
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* Option Register III
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* (Always available, OPTION_MSW, Offset 0x06)
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*/
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#define HP100_PRIORITY_TX 0x0080 /* 1:Do all Tx pkts as priority */
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#define HP100_EE_LOAD 0x0040 /* 1:EEPROM loading, 0 when done */
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#define HP100_ADV_NXT_PKT 0x0004 /* 1:Advance to next pkt in Rx queue */
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/* h/w will set to 0 when done */
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#define HP100_TX_CMD 0x0002 /* 1:Tell h/w download done, h/w */
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/* will set to 0 when done */
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/*
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* Interrupt Status Registers I and II
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* (Page PERFORMANCE, IRQ_STATUS, Offset 0x08-0x09)
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* Note: With old chips, these Registers will clear when 1 is written to them
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* with new chips this depends on setting of CLR_ISMODE
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*/
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#define HP100_RX_EARLY_INT 0x2000
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#define HP100_RX_PDA_ZERO 0x1000
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#define HP100_RX_PDL_FILL_COMPL 0x0800
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#define HP100_RX_PACKET 0x0400 /* 0:No, 1:Yes pkt has been Rx */
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#define HP100_RX_ERROR 0x0200 /* 0:No, 1:Yes Rx pkt had error */
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#define HP100_TX_PDA_ZERO 0x0020 /* 1 when PDA count goes to zero */
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#define HP100_TX_SPACE_AVAIL 0x0010 /* 0:<8192, 1:>=8192 Tx free bytes */
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#define HP100_TX_COMPLETE 0x0008 /* 0:No, 1:Yes a Tx has completed */
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#define HP100_MISC_ERROR 0x0004 /* 0:No, 1:Lan Link down or bus error */
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#define HP100_TX_ERROR 0x0002 /* 0:No, 1:Yes Tx pkt had error */
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/*
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* Xmit Memory Free Count
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* (Page PERFORMANCE, TX_MEM_FREE, Offset 0x14) (Read only, 32bit)
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*/
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#define HP100_AUTO_COMPARE 0x80000000 /* Tx Space avail & pkts<255 */
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#define HP100_FREE_SPACE 0x7fffffe0 /* Tx free memory */
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/*
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* IRQ Channel
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* (Page HW_MAP, IRQ_CHANNEL, Offset 0x0d)
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*/
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#define HP100_ZERO_WAIT_EN 0x80 /* 0:No, 1:Yes asserts NOWS signal */
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#define HP100_IRQ_SCRAMBLE 0x40
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#define HP100_BOND_HP 0x20
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#define HP100_LEVEL_IRQ 0x10 /* 0:Edge, 1:Level type interrupts. */
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/* (Only valid on EISA cards) */
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#define HP100_IRQMASK 0x0F /* Isolate the IRQ bits */
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/*
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* SRAM Parameters
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* (Page HW_MAP, SRAM, Offset 0x0e)
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*/
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#define HP100_RAM_SIZE_MASK 0xe0 /* AND to get SRAM size index */
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#define HP100_RAM_SIZE_SHIFT 0x05 /* Shift count(put index in lwr bits) */
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/*
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* Bus Master Register
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* (Page HW_MAP, BM, Offset 0x0f)
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*/
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#define HP100_BM_BURST_RD 0x01 /* EISA only: 1=Use burst trans. fm system */
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/* memory to chip (tx) */
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#define HP100_BM_BURST_WR 0x02 /* EISA only: 1=Use burst trans. fm system */
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/* memory to chip (rx) */
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#define HP100_BM_MASTER 0x04 /* 0:Slave, 1:BM mode */
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#define HP100_BM_PAGE_CK 0x08 /* This bit should be set whenever in */
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/* an EISA system */
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#define HP100_BM_PCI_8CLK 0x40 /* ... cycles 8 clocks apart */
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/*
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* Mode Control Register I
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* (Page HW_MAP, MODECTRL1, Offset0x10)
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*/
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#define HP100_TX_DUALQ 0x10
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/* If set and BM -> dual tx pda queues */
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#define HP100_ISR_CLRMODE 0x02 /* If set ISR will clear all pending */
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/* interrupts on read (etr only?) */
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#define HP100_EE_NOLOAD 0x04 /* Status whether res will be loaded */
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/* from the eeprom */
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#define HP100_TX_CNT_FLG 0x08 /* Controls Early TX Reg Cnt Field */
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#define HP100_PDL_USE3 0x10 /* If set BM engine will read only */
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/* first three data elements of a PDL */
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/* on the first access. */
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#define HP100_BUSTYPE_MASK 0xe0 /* Three bit bus type info */
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/*
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* Mode Control Register II
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* (Page HW_MAP, MODECTRL2, Offset0x11)
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*/
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#define HP100_EE_MASK 0x0f /* Tell EEPROM circuit not to load */
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/* certain resources */
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#define HP100_DIS_CANCEL 0x20 /* For tx dualq mode operation */
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#define HP100_EN_PDL_WB 0x40 /* 1: Status of PDL completion may be */
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/* written back to system mem */
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#define HP100_EN_BUS_FAIL 0x80 /* Enables bus-fail portion of misc */
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/* interrupt */
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/*
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* PCI Configuration and Control Register I
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* (Page HW_MAP, PCICTRL1, Offset 0x12)
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*/
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#define HP100_LO_MEM 0x01 /* 1: Mapped Mem requested below 1MB */
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#define HP100_NO_MEM 0x02 /* 1: Disables Req for sysmem to PCI */
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/* bios */
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#define HP100_USE_ISA 0x04 /* 1: isa type decodes will occur */
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/* simultaneously with PCI decodes */
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#define HP100_IRQ_HI_MASK 0xf0 /* pgmed by pci bios */
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#define HP100_PCI_IRQ_HI_MASK 0x78 /* Isolate 4 bits for PCI IRQ */
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/*
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* PCI Configuration and Control Register II
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* (Page HW_MAP, PCICTRL2, Offset 0x13)
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*/
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#define HP100_RD_LINE_PDL 0x01 /* 1: PCI command Memory Read Line en */
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#define HP100_RD_TX_DATA_MASK 0x06 /* choose PCI memread cmds for TX */
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#define HP100_MWI 0x08 /* 1: en. PCI memory write invalidate */
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#define HP100_ARB_MODE 0x10 /* Select PCI arbitor type */
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#define HP100_STOP_EN 0x20 /* Enables PCI state machine to issue */
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/* pci stop if cascade not ready */
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#define HP100_IGNORE_PAR 0x40 /* 1: PCI state machine ignores parity */
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#define HP100_PCI_RESET 0x80 /* 0->1: Reset PCI block */
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/*
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* Early TX Configuration and Control Register
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* (Page HW_MAP, EARLYTXCFG, Offset 0x16)
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*/
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#define HP100_EN_EARLY_TX 0x8000 /* 1=Enable Early TX */
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#define HP100_EN_ADAPTIVE 0x4000 /* 1=Enable adaptive mode */
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#define HP100_EN_TX_UR_IRQ 0x2000 /* reserved, must be 0 */
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#define HP100_EN_LOW_TX 0x1000 /* reserved, must be 0 */
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#define HP100_ET_CNT_MASK 0x0fff /* bits 11..0: ET counters */
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/*
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* Early RX Configuration and Control Register
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* (Page HW_MAP, EARLYRXCFG, Offset 0x18)
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*/
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#define HP100_EN_EARLY_RX 0x80 /* 1=Enable Early RX */
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#define HP100_EN_LOW_RX 0x40 /* reserved, must be 0 */
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#define HP100_RX_TRIP_MASK 0x1f /* bits 4..0: threshold at which the
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* early rx circuit will start the
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* dma of received packet into system
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* memory for BM */
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/*
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* Serial Devices Control Register
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* (Page EEPROM_CTRL, EEPROM_CTRL, Offset 0x08)
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*/
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#define HP100_EEPROM_LOAD 0x0001 /* 0->1 loads EEPROM into registers. */
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/* When it goes back to 0, load is */
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/* complete. This should take ~600us. */
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/*
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* 10MB LAN Control and Configuration Register I
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* (Page MAC_CTRL, 10_LAN_CFG_1, Offset 0x08)
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*/
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#define HP100_MAC10_SEL 0xc0 /* Get bits to indicate MAC */
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#define HP100_AUI_SEL 0x20 /* Status of AUI selection */
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#define HP100_LOW_TH 0x10 /* 0:No, 1:Yes allow better cabling */
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#define HP100_LINK_BEAT_DIS 0x08 /* 0:Enable, 1:Disable link beat */
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#define HP100_LINK_BEAT_ST 0x04 /* 0:No, 1:Yes link beat being Rx */
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#define HP100_R_ROL_ST 0x02 /* 0:No, 1:Yes Rx twisted pair has */
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/* been reversed */
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#define HP100_AUI_ST 0x01 /* 0:No, 1:Yes use AUI on TP card */
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/*
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* 10 MB LAN Control and Configuration Register II
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* (Page MAC_CTRL, 10_LAN_CFG_2, Offset 0x09)
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*/
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#define HP100_SQU_ST 0x01 /* 0:No, 1:Yes collision signal sent */
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/* after Tx.Only used for AUI. */
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#define HP100_FULLDUP 0x02 /* 1: LXT901 XCVR fullduplx enabled */
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#define HP100_DOT3_MAC 0x04 /* 1: DOT 3 Mac sel. unless Autosel */
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|
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/*
|
|
* MAC Selection, use with MAC10_SEL bits
|
|
*/
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|
#define HP100_AUTO_SEL_10 0x0 /* Auto select */
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#define HP100_XCVR_LXT901_10 0x1 /* LXT901 10BaseT transceiver */
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#define HP100_XCVR_7213 0x2 /* 7213 transceiver */
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#define HP100_XCVR_82503 0x3 /* 82503 transceiver */
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|
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/*
|
|
* 100MB LAN Training Register
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* (Page MAC_CTRL, VG_LAN_CFG_2, Offset 0x0b) (old, pre 802.12)
|
|
*/
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|
#define HP100_FRAME_FORMAT 0x08 /* 0:802.3, 1:802.5 frames */
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#define HP100_BRIDGE 0x04 /* 0:No, 1:Yes tell hub i am a bridge */
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#define HP100_PROM_MODE 0x02 /* 0:No, 1:Yes tell hub card is */
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/* promiscuous */
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|
#define HP100_REPEATER 0x01 /* 0:No, 1:Yes tell hub MAC wants to */
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/* be a cascaded repeater */
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|
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/*
|
|
* 100MB LAN Control and Configuration Register
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* (Page MAC_CTRL, VG_LAN_CFG_1, Offset 0x0a)
|
|
*/
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|
#define HP100_VG_SEL 0x80 /* 0:No, 1:Yes use 100 Mbit MAC */
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#define HP100_LINK_UP_ST 0x40 /* 0:No, 1:Yes endnode logged in */
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#define HP100_LINK_CABLE_ST 0x20 /* 0:No, 1:Yes cable can hear tones */
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|
/* from hub */
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|
#define HP100_LOAD_ADDR 0x10 /* 0->1 card addr will be sent */
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/* 100ms later the link status */
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|
/* bits are valid */
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|
#define HP100_LINK_CMD 0x08 /* 0->1 link will attempt to log in. */
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/* 100ms later the link status */
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|
/* bits are valid */
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|
#define HP100_TRN_DONE 0x04 /* NEW ETR-Chips only: Will be reset */
|
|
/* after LinkUp Cmd is given and set */
|
|
/* when training has completed. */
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|
#define HP100_LINK_GOOD_ST 0x02 /* 0:No, 1:Yes cable passed training */
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|
#define HP100_VG_RESET 0x01 /* 0:Yes, 1:No reset the 100VG MAC */
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|
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/*
|
|
* MAC Configuration Register I
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|
* (Page MAC_CTRL, MAC_CFG_1, Offset 0x0c)
|
|
*/
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|
#define HP100_RX_IDLE 0x80 /* 0:Yes, 1:No currently receiving pkts */
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#define HP100_TX_IDLE 0x40 /* 0:Yes, 1:No currently Txing pkts */
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|
#define HP100_RX_EN 0x20 /* 1: allow receiving of pkts */
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|
#define HP100_TX_EN 0x10 /* 1: allow transmitting of pkts */
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#define HP100_ACC_ERRORED 0x08 /* 0:No, 1:Yes allow Rx of errored pkts */
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|
#define HP100_ACC_MC 0x04 /* 0:No, 1:Yes allow Rx of multicast pkts */
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|
#define HP100_ACC_BC 0x02 /* 0:No, 1:Yes allow Rx of broadcast pkts */
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|
#define HP100_ACC_PHY 0x01 /* 0:No, 1:Yes allow Rx of ALL phys. pkts */
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|
#define HP100_MAC1MODEMASK 0xf0 /* Hide ACC bits */
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|
#define HP100_MAC1MODE1 0x00 /* Receive nothing, must also disable RX */
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|
#define HP100_MAC1MODE2 0x00
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|
#define HP100_MAC1MODE3 HP100_MAC1MODE2 | HP100_ACC_BC
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|
#define HP100_MAC1MODE4 HP100_MAC1MODE3 | HP100_ACC_MC
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|
#define HP100_MAC1MODE5 HP100_MAC1MODE4 /* set mc hash to all ones also */
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|
#define HP100_MAC1MODE6 HP100_MAC1MODE5 | HP100_ACC_PHY /* Promiscuous */
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|
/* Note MODE6 will receive all GOOD packets on the LAN. This really needs
|
|
a mode 7 defined to be LAN Analyzer mode, which will receive errored and
|
|
runt packets, and keep the CRC bytes. */
|
|
#define HP100_MAC1MODE7 HP100_MAC1MODE6 | HP100_ACC_ERRORED
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|
|
/*
|
|
* MAC Configuration Register II
|
|
* (Page MAC_CTRL, MAC_CFG_2, Offset 0x0d)
|
|
*/
|
|
#define HP100_TR_MODE 0x80 /* 0:No, 1:Yes support Token Ring formats */
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|
#define HP100_TX_SAME 0x40 /* 0:No, 1:Yes Tx same packet continuous */
|
|
#define HP100_LBK_XCVR 0x20 /* 0:No, 1:Yes loopback through MAC & */
|
|
/* transceiver */
|
|
#define HP100_LBK_MAC 0x10 /* 0:No, 1:Yes loopback through MAC */
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|
#define HP100_CRC_I 0x08 /* 0:No, 1:Yes inhibit CRC on Tx packets */
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|
#define HP100_ACCNA 0x04 /* 1: For 802.5: Accept only token ring
|
|
* group addr that maches NA mask */
|
|
#define HP100_KEEP_CRC 0x02 /* 0:No, 1:Yes keep CRC on Rx packets. */
|
|
/* The length will reflect this. */
|
|
#define HP100_ACCFA 0x01 /* 1: For 802.5: Accept only functional
|
|
* addrs that match FA mask (page1) */
|
|
#define HP100_MAC2MODEMASK 0x02
|
|
#define HP100_MAC2MODE1 0x00
|
|
#define HP100_MAC2MODE2 0x00
|
|
#define HP100_MAC2MODE3 0x00
|
|
#define HP100_MAC2MODE4 0x00
|
|
#define HP100_MAC2MODE5 0x00
|
|
#define HP100_MAC2MODE6 0x00
|
|
#define HP100_MAC2MODE7 KEEP_CRC
|
|
|
|
/*
|
|
* MAC Configuration Register III
|
|
* (Page MAC_CTRL, MAC_CFG_3, Offset 0x0e)
|
|
*/
|
|
#define HP100_PACKET_PACE 0x03 /* Packet Pacing:
|
|
* 00: No packet pacing
|
|
* 01: 8 to 16 uS delay
|
|
* 10: 16 to 32 uS delay
|
|
* 11: 32 to 64 uS delay
|
|
*/
|
|
#define HP100_LRF_EN 0x04 /* 1: External LAN Rcv Filter and
|
|
* TCP/IP Checksumming enabled. */
|
|
#define HP100_AUTO_MODE 0x10 /* 1: AutoSelect between 10/100 */
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|
|
|
/*
|
|
* MAC Configuration Register IV
|
|
* (Page MAC_CTRL, MAC_CFG_4, Offset 0x0f)
|
|
*/
|
|
#define HP100_MAC_SEL_ST 0x01 /* (R): Status of external VGSEL
|
|
* Signal, 1=100VG, 0=10Mbit sel. */
|
|
#define HP100_LINK_FAIL_ST 0x02 /* (R): Status of Link Fail portion
|
|
* of the Misc. Interrupt */
|
|
|
|
/*
|
|
* 100 MB LAN Training Request/Allowed Registers
|
|
* (Page MAC_CTRL, TRAIN_REQUEST and TRAIN_ALLOW, Offset 0x14-0x16)(ETR parts only)
|
|
*/
|
|
#define HP100_MACRQ_REPEATER 0x0001 /* 1: MAC tells HUB it wants to be
|
|
* a cascaded repeater
|
|
* 0: ... wants to be a DTE */
|
|
#define HP100_MACRQ_PROMSC 0x0006 /* 2 bits: Promiscious mode
|
|
* 00: Rcv only unicast packets
|
|
* specifically addr to this
|
|
* endnode
|
|
* 10: Rcv all pckts fwded by
|
|
* the local repeater */
|
|
#define HP100_MACRQ_FRAMEFMT_EITHER 0x0018 /* 11: either format allowed */
|
|
#define HP100_MACRQ_FRAMEFMT_802_3 0x0000 /* 00: 802.3 is requested */
|
|
#define HP100_MACRQ_FRAMEFMT_802_5 0x0010 /* 10: 802.5 format is requested */
|
|
#define HP100_CARD_MACVER 0xe000 /* R: 3 bit Cards 100VG MAC version */
|
|
#define HP100_MALLOW_REPEATER 0x0001 /* If reset, requested access as an
|
|
* end node is allowed */
|
|
#define HP100_MALLOW_PROMSC 0x0004 /* 2 bits: Promiscious mode
|
|
* 00: Rcv only unicast packets
|
|
* specifically addr to this
|
|
* endnode
|
|
* 10: Rcv all pckts fwded by
|
|
* the local repeater */
|
|
#define HP100_MALLOW_FRAMEFMT 0x00e0 /* 2 bits: Frame Format
|
|
* 00: 802.3 format will be used
|
|
* 10: 802.5 format will be used */
|
|
#define HP100_MALLOW_ACCDENIED 0x0400 /* N bit */
|
|
#define HP100_MALLOW_CONFIGURE 0x0f00 /* C bit */
|
|
#define HP100_MALLOW_DUPADDR 0x1000 /* D bit */
|
|
#define HP100_HUB_MACVER 0xe000 /* R: 3 bit 802.12 MAC/RMAC training */
|
|
/* protocol of repeater */
|
|
|
|
/* ****************************************************************************** */
|
|
|
|
/*
|
|
* Set/Reset bits
|
|
*/
|
|
#define HP100_SET_HB 0x0100 /* 0:Set fields to 0 whose mask is 1 */
|
|
#define HP100_SET_LB 0x0001 /* HB sets upper byte, LB sets lower byte */
|
|
#define HP100_RESET_HB 0x0000 /* For readability when resetting bits */
|
|
#define HP100_RESET_LB 0x0000 /* For readability when resetting bits */
|
|
|
|
/*
|
|
* Misc. Constants
|
|
*/
|
|
#define HP100_LAN_100 100 /* lan_type value for VG */
|
|
#define HP100_LAN_10 10 /* lan_type value for 10BaseT */
|
|
#define HP100_LAN_COAX 9 /* lan_type value for Coax */
|
|
#define HP100_LAN_ERR (-1) /* lan_type value for link down */
|
|
|
|
/*
|
|
* Bus Master Data Structures ----------------------------------------------
|
|
*/
|
|
|
|
#define MAX_RX_PDL 30 /* Card limit = 31 */
|
|
#define MAX_RX_FRAG 2 /* Don't need more... */
|
|
#define MAX_TX_PDL 29
|
|
#define MAX_TX_FRAG 2 /* Limit = 31 */
|
|
|
|
/* Define total PDL area size in bytes (should be 4096) */
|
|
/* This is the size of kernel (dma) memory that will be allocated. */
|
|
#define MAX_RINGSIZE ((MAX_RX_FRAG*8+4+4)*MAX_RX_PDL+(MAX_TX_FRAG*8+4+4)*MAX_TX_PDL)+16
|
|
|
|
/* Ethernet Packet Sizes */
|
|
#define MIN_ETHER_SIZE 60
|
|
#define MAX_ETHER_SIZE 1514 /* Needed for preallocation of */
|
|
/* skb buffer when busmastering */
|
|
|
|
/* Tx or Rx Ring Entry */
|
|
typedef struct hp100_ring {
|
|
u_int *pdl; /* Address of PDLs PDH, dword before
|
|
* this address is used for rx hdr */
|
|
u_int pdl_paddr; /* Physical address of PDL */
|
|
struct sk_buff *skb;
|
|
struct hp100_ring *next;
|
|
} hp100_ring_t;
|
|
|
|
|
|
|
|
/* Mask for Header Descriptor */
|
|
#define HP100_PKT_LEN_MASK 0x1FFF /* AND with RxLength to get length */
|
|
|
|
|
|
/* Receive Packet Status. Note, the error bits are only valid if ACC_ERRORED
|
|
bit in the MAC Configuration Register 1 is set. */
|
|
#define HP100_RX_PRI 0x8000 /* 0:No, 1:Yes packet is priority */
|
|
#define HP100_SDF_ERR 0x4000 /* 0:No, 1:Yes start of frame error */
|
|
#define HP100_SKEW_ERR 0x2000 /* 0:No, 1:Yes skew out of range */
|
|
#define HP100_BAD_SYMBOL_ERR 0x1000 /* 0:No, 1:Yes invalid symbol received */
|
|
#define HP100_RCV_IPM_ERR 0x0800 /* 0:No, 1:Yes pkt had an invalid packet */
|
|
/* marker */
|
|
#define HP100_SYMBOL_BAL_ERR 0x0400 /* 0:No, 1:Yes symbol balance error */
|
|
#define HP100_VG_ALN_ERR 0x0200 /* 0:No, 1:Yes non-octet received */
|
|
#define HP100_TRUNC_ERR 0x0100 /* 0:No, 1:Yes the packet was truncated */
|
|
#define HP100_RUNT_ERR 0x0040 /* 0:No, 1:Yes pkt length < Min Pkt */
|
|
/* Length Reg. */
|
|
#define HP100_ALN_ERR 0x0010 /* 0:No, 1:Yes align error. */
|
|
#define HP100_CRC_ERR 0x0008 /* 0:No, 1:Yes CRC occurred. */
|
|
|
|
/* The last three bits indicate the type of destination address */
|
|
|
|
#define HP100_MULTI_ADDR_HASH 0x0006 /* 110: Addr multicast, matched hash */
|
|
#define HP100_BROADCAST_ADDR 0x0003 /* x11: Addr broadcast */
|
|
#define HP100_MULTI_ADDR_NO_HASH 0x0002 /* 010: Addr multicast, didn't match hash */
|
|
#define HP100_PHYS_ADDR_MATCH 0x0001 /* x01: Addr was physical and mine */
|
|
#define HP100_PHYS_ADDR_NO_MATCH 0x0000 /* x00: Addr was physical but not mine */
|
|
|
|
/*
|
|
* macros
|
|
*/
|
|
|
|
#define hp100_inb( reg ) \
|
|
inb( ioaddr + HP100_REG_##reg )
|
|
#define hp100_inw( reg ) \
|
|
inw( ioaddr + HP100_REG_##reg )
|
|
#define hp100_inl( reg ) \
|
|
inl( ioaddr + HP100_REG_##reg )
|
|
#define hp100_outb( data, reg ) \
|
|
outb( data, ioaddr + HP100_REG_##reg )
|
|
#define hp100_outw( data, reg ) \
|
|
outw( data, ioaddr + HP100_REG_##reg )
|
|
#define hp100_outl( data, reg ) \
|
|
outl( data, ioaddr + HP100_REG_##reg )
|
|
#define hp100_orb( data, reg ) \
|
|
outb( inb( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg )
|
|
#define hp100_orw( data, reg ) \
|
|
outw( inw( ioaddr + HP100_REG_##reg ) | (data), ioaddr + HP100_REG_##reg )
|
|
#define hp100_andb( data, reg ) \
|
|
outb( inb( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg )
|
|
#define hp100_andw( data, reg ) \
|
|
outw( inw( ioaddr + HP100_REG_##reg ) & (data), ioaddr + HP100_REG_##reg )
|
|
|
|
#define hp100_page( page ) \
|
|
outw( HP100_PAGE_##page, ioaddr + HP100_REG_PAGING )
|
|
#define hp100_ints_off() \
|
|
outw( HP100_INT_EN | HP100_RESET_LB, ioaddr + HP100_REG_OPTION_LSW )
|
|
#define hp100_ints_on() \
|
|
outw( HP100_INT_EN | HP100_SET_LB, ioaddr + HP100_REG_OPTION_LSW )
|
|
#define hp100_mem_map_enable() \
|
|
outw( HP100_MMAP_DIS | HP100_RESET_HB, ioaddr + HP100_REG_OPTION_LSW )
|
|
#define hp100_mem_map_disable() \
|
|
outw( HP100_MMAP_DIS | HP100_SET_HB, ioaddr + HP100_REG_OPTION_LSW )
|