f80dff9da0
get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
113 lines
2.3 KiB
ArmAsm
113 lines
2.3 KiB
ArmAsm
/*
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* include/asm-arm/arch-ebsa285/entry-macro.S
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*
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* Low-level IRQ helper macros for footbridge-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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#include <asm/hardware/dec21285.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.equ dc21285_high, ARMCSR_BASE & 0xff000000
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.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mov r4, #dc21285_high
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.if dc21285_low
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orr r4, r4, #dc21285_low
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.endif
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ldr \irqstat, [r4, #0x180] @ get interrupts
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mov \irqnr, #IRQ_SDRAMPARITY
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tst \irqstat, #IRQ_MASK_SDRAMPARITY
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bne 1001f
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tst \irqstat, #IRQ_MASK_UART_RX
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movne \irqnr, #IRQ_CONRX
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bne 1001f
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tst \irqstat, #IRQ_MASK_DMA1
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movne \irqnr, #IRQ_DMA1
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bne 1001f
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tst \irqstat, #IRQ_MASK_DMA2
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movne \irqnr, #IRQ_DMA2
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bne 1001f
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tst \irqstat, #IRQ_MASK_IN0
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movne \irqnr, #IRQ_IN0
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bne 1001f
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tst \irqstat, #IRQ_MASK_IN1
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movne \irqnr, #IRQ_IN1
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bne 1001f
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tst \irqstat, #IRQ_MASK_IN2
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movne \irqnr, #IRQ_IN2
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bne 1001f
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tst \irqstat, #IRQ_MASK_IN3
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movne \irqnr, #IRQ_IN3
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bne 1001f
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tst \irqstat, #IRQ_MASK_PCI
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movne \irqnr, #IRQ_PCI
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bne 1001f
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tst \irqstat, #IRQ_MASK_DOORBELLHOST
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movne \irqnr, #IRQ_DOORBELLHOST
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bne 1001f
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tst \irqstat, #IRQ_MASK_I2OINPOST
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movne \irqnr, #IRQ_I2OINPOST
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bne 1001f
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tst \irqstat, #IRQ_MASK_TIMER1
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movne \irqnr, #IRQ_TIMER1
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bne 1001f
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tst \irqstat, #IRQ_MASK_TIMER2
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movne \irqnr, #IRQ_TIMER2
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bne 1001f
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tst \irqstat, #IRQ_MASK_TIMER3
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movne \irqnr, #IRQ_TIMER3
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bne 1001f
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tst \irqstat, #IRQ_MASK_UART_TX
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movne \irqnr, #IRQ_CONTX
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bne 1001f
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tst \irqstat, #IRQ_MASK_PCI_ABORT
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movne \irqnr, #IRQ_PCI_ABORT
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bne 1001f
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tst \irqstat, #IRQ_MASK_PCI_SERR
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movne \irqnr, #IRQ_PCI_SERR
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bne 1001f
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tst \irqstat, #IRQ_MASK_DISCARD_TIMER
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movne \irqnr, #IRQ_DISCARD_TIMER
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bne 1001f
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tst \irqstat, #IRQ_MASK_PCI_DPERR
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movne \irqnr, #IRQ_PCI_DPERR
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bne 1001f
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tst \irqstat, #IRQ_MASK_PCI_PERR
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movne \irqnr, #IRQ_PCI_PERR
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1001:
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.endm
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