999304be11
This patch adds setup code for Samsung OneNAND controller driver. The driver needs to be aware on which SoC it is running, so the actual device id is being changed in cpu init code. S3C64xx SoCs have 2 OneNAND controllers while S5PC100 and S5PC110 has only one. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [ben-linux@fluff.org: sort map.h entries] Signed-off-by: Ben Dooks <ben-linux@fluff.org>
96 lines
2.2 KiB
C
96 lines
2.2 KiB
C
/* linux/arch/arm/mach-s3c64xx/s3c6410.c
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*
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* Copyright 2008 Simtec Electronics
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <plat/cpu-freq.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/clock.h>
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#include <plat/sdhci.h>
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#include <plat/iic-core.h>
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#include <plat/adc.h>
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#include <plat/onenand-core.h>
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#include <mach/s3c6400.h>
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#include <mach/s3c6410.h>
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void __init s3c6410_map_io(void)
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{
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/* initialise device information early */
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s3c6410_default_sdhci0();
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s3c6410_default_sdhci1();
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s3c6410_default_sdhci2();
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/* the i2c devices are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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s3c_i2c1_setname("s3c2440-i2c");
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s3c_device_adc.name = "s3c64xx-adc";
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s3c_device_nand.name = "s3c6400-nand";
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s3c_onenand_setname("s3c6410-onenand");
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s3c64xx_onenand1_setname("s3c6410-onenand");
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}
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void __init s3c6410_init_clocks(int xtal)
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{
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printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
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s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
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s3c6400_setup_clocks();
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}
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void __init s3c6410_init_irq(void)
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{
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/* VIC0 is missing IRQ7, VIC1 is fully populated. */
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s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
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}
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struct sysdev_class s3c6410_sysclass = {
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.name = "s3c6410-core",
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};
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static struct sys_device s3c6410_sysdev = {
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.cls = &s3c6410_sysclass,
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};
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static int __init s3c6410_core_init(void)
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{
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return sysdev_class_register(&s3c6410_sysclass);
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}
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core_initcall(s3c6410_core_init);
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int __init s3c6410_init(void)
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{
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printk("S3C6410: Initialising architecture\n");
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return sysdev_register(&s3c6410_sysdev);
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}
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