2e1ee1f766
Implement deep-sleep on MPC52xx. SDRAM is put into self-refresh with help of SRAM code (alternatives would be code in FLASH, I-cache). Interrupt code must also not be in SDRAM, so put it in I-cache. MPC52xx core is static, so contents will remain intact even with clocks turned off. Signed-off-by: Domen Puncer <domen.puncer@telargo.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
154 lines
2.5 KiB
ArmAsm
154 lines
2.5 KiB
ArmAsm
#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/processor.h>
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.text
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_GLOBAL(mpc52xx_deep_sleep)
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mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
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/* enable interrupts */
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mfmsr r7
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ori r7, r7, 0x8000 /* EE */
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mtmsr r7
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sync; isync;
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li r10, 0 /* flag that irq handler sets */
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/* enable tmr7 (or any other) interrupt */
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lwz r8, 0x14(r6) /* intr->main_mask */
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ori r8, r8, 0x1
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xori r8, r8, 0x1
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stw r8, 0x14(r6)
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sync
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/* emulate tmr7 interrupt */
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li r8, 0x1
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stw r8, 0x40(r6) /* intr->main_emulate */
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sync
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/* wait for it to happen */
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1:
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cmpi cr0, r10, 1
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bne cr0, 1b
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/* lock icache */
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mfspr r10, SPRN_HID0
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ori r10, r10, 0x2000
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sync; isync;
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mtspr SPRN_HID0, r10
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sync; isync;
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mflr r9 /* save LR */
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/* jump to sram */
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mtlr r3
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blrl
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mtlr r9 /* restore LR */
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/* unlock icache */
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mfspr r10, SPRN_HID0
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ori r10, r10, 0x2000
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xori r10, r10, 0x2000
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sync; isync;
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mtspr SPRN_HID0, r10
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sync; isync;
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/* return to C code */
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blr
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_GLOBAL(mpc52xx_ds_sram)
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mpc52xx_ds_sram:
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/* put SDRAM into self-refresh */
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lwz r8, 0x4(r4) /* sdram->ctrl */
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oris r8, r8, 0x8000 /* mode_en */
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stw r8, 0x4(r4)
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sync
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ori r8, r8, 0x0002 /* soft_pre */
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stw r8, 0x4(r4)
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sync
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xori r8, r8, 0x0002
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xoris r8, r8, 0x8000 /* !mode_en */
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stw r8, 0x4(r4)
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sync
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oris r8, r8, 0x5000
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xoris r8, r8, 0x4000 /* ref_en !cke */
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stw r8, 0x4(r4)
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sync
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/* disable SDRAM clock */
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lwz r8, 0x14(r5) /* cdm->clkenable */
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ori r8, r8, 0x0008
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xori r8, r8, 0x0008
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stw r8, 0x14(r5)
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sync
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/* put mpc5200 to sleep */
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mfmsr r10
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oris r10, r10, 0x0004 /* POW = 1 */
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sync; isync;
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mtmsr r10
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sync; isync;
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/* enable clock */
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lwz r8, 0x14(r5)
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ori r8, r8, 0x0008
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stw r8, 0x14(r5)
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sync
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/* get ram out of self-refresh */
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lwz r8, 0x4(r4)
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oris r8, r8, 0x5000 /* cke ref_en */
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stw r8, 0x4(r4)
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sync
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blr
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_GLOBAL(mpc52xx_ds_sram_size)
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mpc52xx_ds_sram_size:
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.long $-mpc52xx_ds_sram
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/* ### interrupt handler for wakeup from deep-sleep ### */
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_GLOBAL(mpc52xx_ds_cached)
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mpc52xx_ds_cached:
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mtspr SPRN_SPRG0, r7
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mtspr SPRN_SPRG1, r8
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/* disable emulated interrupt */
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mfspr r7, 311 /* MBAR */
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addi r7, r7, 0x540 /* intr->main_emul */
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li r8, 0
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stw r8, 0(r7)
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sync
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dcbf 0, r7
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/* acknowledge wakeup, so CCS releases power pown */
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mfspr r7, 311 /* MBAR */
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addi r7, r7, 0x524 /* intr->enc_status */
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lwz r8, 0(r7)
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ori r8, r8, 0x0400
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stw r8, 0(r7)
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sync
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dcbf 0, r7
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/* flag - we handled the interrupt */
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li r10, 1
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mfspr r8, SPRN_SPRG1
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mfspr r7, SPRN_SPRG0
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rfi
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_GLOBAL(mpc52xx_ds_cached_size)
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mpc52xx_ds_cached_size:
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.long $-mpc52xx_ds_cached
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