75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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void
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nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t limit = max(1u, addr + size) - 1;
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if (pitch)
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addr |= 1;
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switch (dev_priv->chipset) {
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case 0x40:
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nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
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nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
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nv_wr32(dev, NV10_PFB_TILE(i), addr);
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break;
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default:
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nv_wr32(dev, NV40_PFB_TLIMIT(i), limit);
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nv_wr32(dev, NV40_PFB_TSIZE(i), pitch);
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nv_wr32(dev, NV40_PFB_TILE(i), addr);
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break;
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}
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}
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int
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nv40_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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uint32_t tmp;
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int i;
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/* This is strictly a NV4x register (don't know about NV5x). */
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/* The blob sets these to all kinds of values, and they mess up our setup. */
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/* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
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/* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
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/* Any idea what this is? */
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nv_wr32(dev, NV40_PFB_UNK_800, 0x1);
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x45:
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tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
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nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
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pfb->num_tiles = NV10_PFB_TILE__SIZE;
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break;
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case 0x46: /* G72 */
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case 0x47: /* G70 */
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case 0x49: /* G71 */
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case 0x4b: /* G73 */
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case 0x4c: /* C51 (G7X version) */
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pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
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break;
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default:
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pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
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break;
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}
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/* Turn all the tiling regions off. */
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->set_region_tiling(dev, i, 0, 0, 0);
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return 0;
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}
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void
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nv40_fb_takedown(struct drm_device *dev)
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{
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}
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