222 lines
7.5 KiB
C
222 lines
7.5 KiB
C
/*
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* (c) 2003-2006 Advanced Micro Devices, Inc.
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* Your use of this code is subject to the terms and conditions of the
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* GNU general public license version 2. See "COPYING" or
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* http://www.gnu.org/licenses/gpl.html
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*/
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enum pstate {
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HW_PSTATE_INVALID = 0xff,
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HW_PSTATE_0 = 0,
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HW_PSTATE_1 = 1,
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HW_PSTATE_2 = 2,
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HW_PSTATE_3 = 3,
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HW_PSTATE_4 = 4,
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HW_PSTATE_5 = 5,
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HW_PSTATE_6 = 6,
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HW_PSTATE_7 = 7,
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};
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struct powernow_k8_data {
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unsigned int cpu;
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u32 numps; /* number of p-states */
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u32 batps; /* number of p-states supported on battery */
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u32 max_hw_pstate; /* maximum legal hardware pstate */
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/* these values are constant when the PSB is used to determine
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* vid/fid pairings, but are modified during the ->target() call
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* when ACPI is used */
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u32 rvo; /* ramp voltage offset */
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u32 irt; /* isochronous relief time */
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u32 vidmvs; /* usable value calculated from mvs */
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u32 vstable; /* voltage stabilization time, units 20 us */
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u32 plllock; /* pll lock time, units 1 us */
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u32 exttype; /* extended interface = 1 */
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/* keep track of the current fid / vid or pstate */
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u32 currvid;
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u32 currfid;
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enum pstate currpstate;
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/* the powernow_table includes all frequency and vid/fid pairings:
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* fid are the lower 8 bits of the index, vid are the upper 8 bits.
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* frequency is in kHz */
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struct cpufreq_frequency_table *powernow_table;
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/* the acpi table needs to be kept. it's only available if ACPI was
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* used to determine valid frequency/vid/fid states */
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struct acpi_processor_performance acpi_data;
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/* we need to keep track of associated cores, but let cpufreq
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* handle hotplug events - so just point at cpufreq pol->cpus
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* structure */
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struct cpumask *available_cores;
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};
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/* processor's cpuid instruction support */
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#define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
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#define CPUID_XFAM 0x0ff00000 /* extended family */
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#define CPUID_XFAM_K8 0
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#define CPUID_XMOD 0x000f0000 /* extended model */
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#define CPUID_XMOD_REV_MASK 0x000c0000
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#define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
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#define CPUID_USE_XFAM_XMOD 0x00000f00
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#define CPUID_GET_MAX_CAPABILITIES 0x80000000
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#define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
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#define P_STATE_TRANSITION_CAPABLE 6
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/* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
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/* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
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/* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
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/* the register number is placed in ecx, and the data is returned in edx:eax. */
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#define MSR_FIDVID_CTL 0xc0010041
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#define MSR_FIDVID_STATUS 0xc0010042
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/* Field definitions within the FID VID Low Control MSR : */
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#define MSR_C_LO_INIT_FID_VID 0x00010000
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#define MSR_C_LO_NEW_VID 0x00003f00
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#define MSR_C_LO_NEW_FID 0x0000003f
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#define MSR_C_LO_VID_SHIFT 8
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/* Field definitions within the FID VID High Control MSR : */
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#define MSR_C_HI_STP_GNT_TO 0x000fffff
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/* Field definitions within the FID VID Low Status MSR : */
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#define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
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#define MSR_S_LO_MAX_RAMP_VID 0x3f000000
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#define MSR_S_LO_MAX_FID 0x003f0000
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#define MSR_S_LO_START_FID 0x00003f00
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#define MSR_S_LO_CURRENT_FID 0x0000003f
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/* Field definitions within the FID VID High Status MSR : */
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#define MSR_S_HI_MIN_WORKING_VID 0x3f000000
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#define MSR_S_HI_MAX_WORKING_VID 0x003f0000
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#define MSR_S_HI_START_VID 0x00003f00
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#define MSR_S_HI_CURRENT_VID 0x0000003f
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#define MSR_C_HI_STP_GNT_BENIGN 0x00000001
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/* Hardware Pstate _PSS and MSR definitions */
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#define USE_HW_PSTATE 0x00000080
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#define HW_PSTATE_MASK 0x00000007
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#define HW_PSTATE_VALID_MASK 0x80000000
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#define HW_PSTATE_MAX_MASK 0x000000f0
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#define HW_PSTATE_MAX_SHIFT 4
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#define MSR_PSTATE_DEF_BASE 0xc0010064 /* base of Pstate MSRs */
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#define MSR_PSTATE_STATUS 0xc0010063 /* Pstate Status MSR */
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#define MSR_PSTATE_CTRL 0xc0010062 /* Pstate control MSR */
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#define MSR_PSTATE_CUR_LIMIT 0xc0010061 /* pstate current limit MSR */
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/* define the two driver architectures */
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#define CPU_OPTERON 0
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#define CPU_HW_PSTATE 1
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/*
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* There are restrictions frequencies have to follow:
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* - only 1 entry in the low fid table ( <=1.4GHz )
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* - lowest entry in the high fid table must be >= 2 * the entry in the
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* low fid table
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* - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
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* in the low fid table
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* - the parts can only step at <= 200 MHz intervals, odd fid values are
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* supported in revision G and later revisions.
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* - lowest frequency must be >= interprocessor hypertransport link speed
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* (only applies to MP systems obviously)
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*/
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/* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
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#define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
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#define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
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#define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
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#define HI_VCOFREQ_TABLE_BOTTOM 1600
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#define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
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#define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
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#define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
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#define MIN_FREQ 800 /* Min and max freqs, per spec */
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#define MAX_FREQ 5000
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#define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
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#define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
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#define VID_OFF 0x3f
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#define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
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#define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
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#define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
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#define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */
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/*
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* Most values of interest are encoded in a single field of the _PSS
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* entries: the "control" value.
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*/
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#define IRT_SHIFT 30
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#define RVO_SHIFT 28
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#define EXT_TYPE_SHIFT 27
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#define PLL_L_SHIFT 20
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#define MVS_SHIFT 18
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#define VST_SHIFT 11
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#define VID_SHIFT 6
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#define IRT_MASK 3
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#define RVO_MASK 3
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#define EXT_TYPE_MASK 1
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#define PLL_L_MASK 0x7f
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#define MVS_MASK 3
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#define VST_MASK 0x7f
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#define VID_MASK 0x1f
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#define FID_MASK 0x1f
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#define EXT_VID_MASK 0x3f
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#define EXT_FID_MASK 0x3f
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/*
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* Version 1.4 of the PSB table. This table is constructed by BIOS and is
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* to tell the OS's power management driver which VIDs and FIDs are
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* supported by this particular processor.
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* If the data in the PSB / PST is wrong, then this driver will program the
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* wrong values into hardware, which is very likely to lead to a crash.
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*/
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#define PSB_ID_STRING "AMDK7PNOW!"
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#define PSB_ID_STRING_LEN 10
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#define PSB_VERSION_1_4 0x14
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struct psb_s {
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u8 signature[10];
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u8 tableversion;
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u8 flags1;
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u16 vstable;
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u8 flags2;
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u8 num_tables;
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u32 cpuid;
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u8 plllocktime;
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u8 maxfid;
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u8 maxvid;
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u8 numps;
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};
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/* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
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struct pst_s {
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u8 fid;
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u8 vid;
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};
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static int core_voltage_pre_transition(struct powernow_k8_data *data,
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u32 reqvid, u32 regfid);
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static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
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static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
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static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
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static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
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static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
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