77bd741561
Various PCI bus errors can be signaled by newer PCI controllers. The core error recovery routines are architecture dependent. This patch adds a recovery infrastructure for the PPC64 pSeries systems. Signed-off-by: Linas Vepstas <linas@austin.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org> (cherry picked from e8ca11b460c4c9c7fa6b529be221529ebd770e38 commit)
383 lines
9.9 KiB
C
383 lines
9.9 KiB
C
/*
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* eeh.h
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* Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _PPC64_EEH_H
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#define _PPC64_EEH_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/string.h>
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struct pci_dev;
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struct device_node;
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#ifdef CONFIG_EEH
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extern int eeh_subsystem_enabled;
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/* Values for eeh_mode bits in device_node */
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#define EEH_MODE_SUPPORTED (1<<0)
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#define EEH_MODE_NOCHECK (1<<1)
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#define EEH_MODE_ISOLATED (1<<2)
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#define EEH_MODE_RECOVERING (1<<3)
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#define EEH_MODE_IRQ_DISABLED (1<<4)
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/* Max number of EEH freezes allowed before we consider the device
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* to be permanently disabled. */
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#define EEH_MAX_ALLOWED_FREEZES 5
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void __init eeh_init(void);
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unsigned long eeh_check_failure(const volatile void __iomem *token,
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unsigned long val);
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int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
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void __init pci_addr_cache_build(void);
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/**
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* eeh_add_device_early
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* eeh_add_device_late
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*
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* Perform eeh initialization for devices added after boot.
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* Call eeh_add_device_early before doing any i/o to the
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* device (including config space i/o). Call eeh_add_device_late
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* to finish the eeh setup for this device.
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*/
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void eeh_add_device_early(struct device_node *);
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void eeh_add_device_tree_early(struct device_node *);
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void eeh_add_device_late(struct pci_dev *);
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/**
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* eeh_remove_device - undo EEH setup for the indicated pci device
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* @dev: pci device to be removed
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*
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* This routine should be called when a device is removed from
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* a running system (e.g. by hotplug or dlpar). It unregisters
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* the PCI device from the EEH subsystem. I/O errors affecting
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* this device will no longer be detected after this call; thus,
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* i/o errors affecting this slot may leave this device unusable.
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*/
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void eeh_remove_device(struct pci_dev *);
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/**
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* eeh_remove_device_recursive - undo EEH for device & children.
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* @dev: pci device to be removed
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*
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* As above, this removes the device; it also removes child
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* pci devices as well.
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*/
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void eeh_remove_bus_device(struct pci_dev *);
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/**
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* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
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*
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* If this macro yields TRUE, the caller relays to eeh_check_failure()
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* which does further tests out of line.
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*/
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#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
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/*
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* Reads from a device which has been isolated by EEH will return
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* all 1s. This macro gives an all-1s value of the given size (in
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* bytes: 1, 2, or 4) for comparing with the result of a read.
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*/
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#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
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#else /* !CONFIG_EEH */
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static inline void eeh_init(void) { }
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static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
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{
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return val;
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}
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static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
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{
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return 0;
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}
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static inline void pci_addr_cache_build(void) { }
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static inline void eeh_add_device_early(struct device_node *dn) { }
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static inline void eeh_add_device_late(struct pci_dev *dev) { }
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static inline void eeh_remove_device(struct pci_dev *dev) { }
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static inline void eeh_add_device_tree_early(struct device_node *dn) { }
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static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
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#define EEH_POSSIBLE_ERROR(val, type) (0)
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#define EEH_IO_ERROR_VALUE(size) (-1UL)
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#endif /* CONFIG_EEH */
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/*
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* MMIO read/write operations with EEH support.
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*/
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static inline u8 eeh_readb(const volatile void __iomem *addr)
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{
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u8 val = in_8(addr);
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if (EEH_POSSIBLE_ERROR(val, u8))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_writeb(u8 val, volatile void __iomem *addr)
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{
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out_8(addr, val);
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}
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static inline u16 eeh_readw(const volatile void __iomem *addr)
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{
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u16 val = in_le16(addr);
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if (EEH_POSSIBLE_ERROR(val, u16))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_writew(u16 val, volatile void __iomem *addr)
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{
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out_le16(addr, val);
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}
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static inline u16 eeh_raw_readw(const volatile void __iomem *addr)
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{
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u16 val = in_be16(addr);
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if (EEH_POSSIBLE_ERROR(val, u16))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_raw_writew(u16 val, volatile void __iomem *addr) {
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volatile u16 __iomem *vaddr = (volatile u16 __iomem *) addr;
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out_be16(vaddr, val);
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}
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static inline u32 eeh_readl(const volatile void __iomem *addr)
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{
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u32 val = in_le32(addr);
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if (EEH_POSSIBLE_ERROR(val, u32))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_writel(u32 val, volatile void __iomem *addr)
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{
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out_le32(addr, val);
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}
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static inline u32 eeh_raw_readl(const volatile void __iomem *addr)
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{
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u32 val = in_be32(addr);
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if (EEH_POSSIBLE_ERROR(val, u32))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_raw_writel(u32 val, volatile void __iomem *addr)
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{
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out_be32(addr, val);
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}
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static inline u64 eeh_readq(const volatile void __iomem *addr)
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{
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u64 val = in_le64(addr);
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if (EEH_POSSIBLE_ERROR(val, u64))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_writeq(u64 val, volatile void __iomem *addr)
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{
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out_le64(addr, val);
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}
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static inline u64 eeh_raw_readq(const volatile void __iomem *addr)
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{
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u64 val = in_be64(addr);
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if (EEH_POSSIBLE_ERROR(val, u64))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_raw_writeq(u64 val, volatile void __iomem *addr)
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{
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out_be64(addr, val);
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}
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#define EEH_CHECK_ALIGN(v,a) \
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((((unsigned long)(v)) & ((a) - 1)) == 0)
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static inline void eeh_memset_io(volatile void __iomem *addr, int c,
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unsigned long n)
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{
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void *p = (void __force *)addr;
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u32 lc = c;
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lc |= lc << 8;
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lc |= lc << 16;
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while(n && !EEH_CHECK_ALIGN(p, 4)) {
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*((volatile u8 *)p) = c;
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p++;
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n--;
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}
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while(n >= 4) {
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*((volatile u32 *)p) = lc;
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p += 4;
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n -= 4;
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}
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while(n) {
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*((volatile u8 *)p) = c;
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p++;
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n--;
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}
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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static inline void eeh_memcpy_fromio(void *dest, const volatile void __iomem *src,
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unsigned long n)
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{
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void *vsrc = (void __force *) src;
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void *destsave = dest;
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unsigned long nsave = n;
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while(n && (!EEH_CHECK_ALIGN(vsrc, 4) || !EEH_CHECK_ALIGN(dest, 4))) {
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*((u8 *)dest) = *((volatile u8 *)vsrc);
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__asm__ __volatile__ ("eieio" : : : "memory");
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vsrc++;
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dest++;
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n--;
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}
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while(n > 4) {
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*((u32 *)dest) = *((volatile u32 *)vsrc);
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__asm__ __volatile__ ("eieio" : : : "memory");
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vsrc += 4;
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dest += 4;
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n -= 4;
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}
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while(n) {
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*((u8 *)dest) = *((volatile u8 *)vsrc);
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__asm__ __volatile__ ("eieio" : : : "memory");
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vsrc++;
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dest++;
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n--;
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}
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__asm__ __volatile__ ("sync" : : : "memory");
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/* Look for ffff's here at dest[n]. Assume that at least 4 bytes
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* were copied. Check all four bytes.
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*/
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if ((nsave >= 4) &&
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(EEH_POSSIBLE_ERROR((*((u32 *) destsave+nsave-4)), u32))) {
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eeh_check_failure(src, (*((u32 *) destsave+nsave-4)));
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}
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}
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static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src,
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unsigned long n)
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{
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void *vdest = (void __force *) dest;
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while(n && (!EEH_CHECK_ALIGN(vdest, 4) || !EEH_CHECK_ALIGN(src, 4))) {
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*((volatile u8 *)vdest) = *((u8 *)src);
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src++;
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vdest++;
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n--;
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}
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while(n > 4) {
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*((volatile u32 *)vdest) = *((volatile u32 *)src);
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src += 4;
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vdest += 4;
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n-=4;
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}
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while(n) {
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*((volatile u8 *)vdest) = *((u8 *)src);
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src++;
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vdest++;
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n--;
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}
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__asm__ __volatile__ ("sync" : : : "memory");
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}
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#undef EEH_CHECK_ALIGN
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static inline u8 eeh_inb(unsigned long port)
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{
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u8 val;
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if (!_IO_IS_VALID(port))
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return ~0;
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val = in_8((u8 __iomem *)(port+pci_io_base));
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if (EEH_POSSIBLE_ERROR(val, u8))
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return eeh_check_failure((void __iomem *)(port), val);
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return val;
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}
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static inline void eeh_outb(u8 val, unsigned long port)
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{
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if (_IO_IS_VALID(port))
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out_8((u8 __iomem *)(port+pci_io_base), val);
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}
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static inline u16 eeh_inw(unsigned long port)
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{
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u16 val;
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if (!_IO_IS_VALID(port))
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return ~0;
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val = in_le16((u16 __iomem *)(port+pci_io_base));
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if (EEH_POSSIBLE_ERROR(val, u16))
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return eeh_check_failure((void __iomem *)(port), val);
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return val;
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}
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static inline void eeh_outw(u16 val, unsigned long port)
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{
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if (_IO_IS_VALID(port))
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out_le16((u16 __iomem *)(port+pci_io_base), val);
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}
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static inline u32 eeh_inl(unsigned long port)
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{
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u32 val;
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if (!_IO_IS_VALID(port))
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return ~0;
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val = in_le32((u32 __iomem *)(port+pci_io_base));
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if (EEH_POSSIBLE_ERROR(val, u32))
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return eeh_check_failure((void __iomem *)(port), val);
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return val;
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}
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static inline void eeh_outl(u32 val, unsigned long port)
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{
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if (_IO_IS_VALID(port))
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out_le32((u32 __iomem *)(port+pci_io_base), val);
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}
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/* in-string eeh macros */
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static inline void eeh_insb(unsigned long port, void * buf, int ns)
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{
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_insb((u8 __iomem *)(port+pci_io_base), buf, ns);
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if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
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eeh_check_failure((void __iomem *)(port), *(u8*)buf);
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}
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static inline void eeh_insw_ns(unsigned long port, void * buf, int ns)
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{
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_insw_ns((u16 __iomem *)(port+pci_io_base), buf, ns);
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if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
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eeh_check_failure((void __iomem *)(port), *(u16*)buf);
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}
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static inline void eeh_insl_ns(unsigned long port, void * buf, int nl)
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{
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_insl_ns((u32 __iomem *)(port+pci_io_base), buf, nl);
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if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
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eeh_check_failure((void __iomem *)(port), *(u32*)buf);
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}
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#endif /* __KERNEL__ */
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#endif /* _PPC64_EEH_H */
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