010c108d7a
The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
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* Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
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*/
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#ifndef _ASM_IRQ_H
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#define _ASM_IRQ_H
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#include <linux/linkage.h>
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#include <linux/smp.h>
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#include <asm/mipsmtregs.h>
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#include <irq.h>
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#ifdef CONFIG_I8259
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static inline int irq_canonicalize(int irq)
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{
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return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
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}
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#else
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#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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struct irqaction;
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extern unsigned long irq_hwmask[];
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extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
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unsigned long hwmask);
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static inline void smtc_im_ack_irq(unsigned int irq)
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{
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if (irq_hwmask[irq] & ST0_IM)
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set_c0_status(irq_hwmask[irq] & ST0_IM);
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}
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#else
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static inline void smtc_im_ack_irq(unsigned int irq)
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{
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}
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#endif /* CONFIG_MIPS_MT_SMTC */
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#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
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#include <linux/cpumask.h>
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extern int plat_set_irq_affinity(unsigned int irq,
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const struct cpumask *affinity);
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extern void smtc_forward_irq(unsigned int irq);
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/*
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* IRQ affinity hook invoked at the beginning of interrupt dispatch
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* if option is enabled.
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*
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* Up through Linux 2.6.22 (at least) cpumask operations are very
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* inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
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* used a "fast path" per-IRQ-descriptor cache of affinity information
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* to reduce latency. As there is a project afoot to optimize the
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* cpumask implementations, this version is optimistically assuming
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* that cpumask.h macro overhead is reasonable during interrupt dispatch.
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*/
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#define IRQ_AFFINITY_HOOK(irq) \
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do { \
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if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\
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smtc_forward_irq(irq); \
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irq_exit(); \
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return; \
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} \
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} while (0)
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#else /* Not doing SMTC affinity */
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#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
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#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
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#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
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/*
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* Clear interrupt mask handling "backstop" if irq_hwmask
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* entry so indicates. This implies that the ack() or end()
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* functions will take over re-enabling the low-level mask.
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* Otherwise it will be done on return from exception.
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*/
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#define __DO_IRQ_SMTC_HOOK(irq) \
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do { \
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IRQ_AFFINITY_HOOK(irq); \
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if (irq_hwmask[irq] & 0x0000ff00) \
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write_c0_tccontext(read_c0_tccontext() & \
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~(irq_hwmask[irq] & 0x0000ff00)); \
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} while (0)
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#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) \
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do { \
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if (irq_hwmask[irq] & 0x0000ff00) \
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write_c0_tccontext(read_c0_tccontext() & \
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~(irq_hwmask[irq] & 0x0000ff00)); \
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} while (0)
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#else
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#define __DO_IRQ_SMTC_HOOK(irq) \
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do { \
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IRQ_AFFINITY_HOOK(irq); \
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} while (0)
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#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
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#endif
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extern void do_IRQ(unsigned int irq);
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#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
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extern void do_IRQ_no_affinity(unsigned int irq);
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#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
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extern void arch_init_irq(void);
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extern void spurious_interrupt(void);
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extern int allocate_irqno(void);
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extern void alloc_legacy_irqno(void);
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extern void free_irqno(unsigned int irq);
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/*
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* Before R2 the timer and performance counter interrupts were both fixed to
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* IE7. Since R2 their number has to be read from the c0_intctl register.
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*/
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#define CP0_LEGACY_COMPARE_IRQ 7
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extern int cp0_compare_irq;
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extern int cp0_compare_irq_shift;
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extern int cp0_perfcount_irq;
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#endif /* _ASM_IRQ_H */
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