466 lines
14 KiB
C
466 lines
14 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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static void
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nv50_fifo_playlist_update(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_gpuobj_ref *cur;
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int i, nr;
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NV_DEBUG(dev, "\n");
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cur = pfifo->playlist[pfifo->cur_playlist];
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pfifo->cur_playlist = !pfifo->cur_playlist;
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/* We never schedule channel 0 or 127 */
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for (i = 1, nr = 0; i < 127; i++) {
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if (dev_priv->fifos[i] && dev_priv->fifos[i]->ramfc)
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nv_wo32(dev, cur->gpuobj, nr++, i);
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}
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dev_priv->engine.instmem.flush(dev);
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nv_wr32(dev, 0x32f4, cur->instance >> 12);
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nv_wr32(dev, 0x32ec, nr);
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nv_wr32(dev, 0x2500, 0x101);
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}
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static void
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nv50_fifo_channel_enable(struct drm_device *dev, int channel)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = dev_priv->fifos[channel];
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uint32_t inst;
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NV_DEBUG(dev, "ch%d\n", channel);
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if (dev_priv->chipset == 0x50)
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inst = chan->ramfc->instance >> 12;
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else
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inst = chan->ramfc->instance >> 8;
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nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst |
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NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
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}
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static void
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nv50_fifo_channel_disable(struct drm_device *dev, int channel)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t inst;
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NV_DEBUG(dev, "ch%d\n", channel);
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if (dev_priv->chipset == 0x50)
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inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
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else
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inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
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nv_wr32(dev, NV50_PFIFO_CTX_TABLE(channel), inst);
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}
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static void
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nv50_fifo_init_reset(struct drm_device *dev)
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{
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uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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nv50_fifo_init_intr(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV03_PFIFO_INTR_0, 0xFFFFFFFF);
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nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
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}
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static void
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nv50_fifo_init_context_table(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i;
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NV_DEBUG(dev, "\n");
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for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++) {
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if (dev_priv->fifos[i])
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nv50_fifo_channel_enable(dev, i);
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else
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nv50_fifo_channel_disable(dev, i);
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}
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nv50_fifo_playlist_update(dev);
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}
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static void
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nv50_fifo_init_regs__nv(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, 0x250c, 0x6f3cfc34);
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}
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static void
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nv50_fifo_init_regs(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, 0x2500, 0);
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nv_wr32(dev, 0x3250, 0);
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nv_wr32(dev, 0x3220, 0);
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nv_wr32(dev, 0x3204, 0);
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nv_wr32(dev, 0x3210, 0);
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nv_wr32(dev, 0x3270, 0);
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/* Enable dummy channels setup by nv50_instmem.c */
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nv50_fifo_channel_enable(dev, 0);
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nv50_fifo_channel_enable(dev, 127);
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}
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int
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nv50_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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int ret;
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NV_DEBUG(dev, "\n");
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if (pfifo->playlist[0]) {
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pfifo->cur_playlist = !pfifo->cur_playlist;
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goto just_reset;
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}
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ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC,
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&pfifo->playlist[0]);
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if (ret) {
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NV_ERROR(dev, "error creating playlist 0: %d\n", ret);
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return ret;
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}
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ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC,
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&pfifo->playlist[1]);
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if (ret) {
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nouveau_gpuobj_ref_del(dev, &pfifo->playlist[0]);
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NV_ERROR(dev, "error creating playlist 1: %d\n", ret);
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return ret;
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}
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just_reset:
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nv50_fifo_init_reset(dev);
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nv50_fifo_init_intr(dev);
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nv50_fifo_init_context_table(dev);
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nv50_fifo_init_regs__nv(dev);
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nv50_fifo_init_regs(dev);
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dev_priv->engine.fifo.enable(dev);
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dev_priv->engine.fifo.reassign(dev, true);
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return 0;
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}
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void
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nv50_fifo_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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NV_DEBUG(dev, "\n");
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if (!pfifo->playlist[0])
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return;
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nouveau_gpuobj_ref_del(dev, &pfifo->playlist[0]);
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nouveau_gpuobj_ref_del(dev, &pfifo->playlist[1]);
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}
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int
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nv50_fifo_channel_id(struct drm_device *dev)
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{
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return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
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NV50_PFIFO_CACHE1_PUSH1_CHID_MASK;
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}
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int
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nv50_fifo_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramfc = NULL;
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unsigned long flags;
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int ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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if (dev_priv->chipset == 0x50) {
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uint32_t ramin_poffset = chan->ramin->gpuobj->im_pramin->start;
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uint32_t ramin_voffset = chan->ramin->gpuobj->im_backing_start;
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ret = nouveau_gpuobj_new_fake(dev, ramin_poffset, ramin_voffset,
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0x100, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &ramfc,
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&chan->ramfc);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_new_fake(dev, ramin_poffset + 0x0400,
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ramin_voffset + 0x0400, 4096,
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0, NULL, &chan->cache);
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if (ret)
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return ret;
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} else {
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&chan->ramfc);
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if (ret)
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return ret;
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ramfc = chan->ramfc->gpuobj;
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
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0, &chan->cache);
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if (ret)
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return ret;
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}
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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nv_wo32(dev, ramfc, 0x48/4, chan->pushbuf->instance >> 4);
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nv_wo32(dev, ramfc, 0x80/4, (0 << 27) /* 4KiB */ |
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(4 << 24) /* SEARCH_FULL */ |
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(chan->ramht->instance >> 4));
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nv_wo32(dev, ramfc, 0x44/4, 0x2101ffff);
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nv_wo32(dev, ramfc, 0x60/4, 0x7fffffff);
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nv_wo32(dev, ramfc, 0x40/4, 0x00000000);
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nv_wo32(dev, ramfc, 0x7c/4, 0x30000001);
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nv_wo32(dev, ramfc, 0x78/4, 0x00000000);
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nv_wo32(dev, ramfc, 0x3c/4, 0x403f6078);
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nv_wo32(dev, ramfc, 0x50/4, chan->pushbuf_base +
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chan->dma.ib_base * 4);
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nv_wo32(dev, ramfc, 0x54/4, drm_order(chan->dma.ib_max + 1) << 16);
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if (dev_priv->chipset != 0x50) {
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nv_wo32(dev, chan->ramin->gpuobj, 0, chan->id);
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nv_wo32(dev, chan->ramin->gpuobj, 1,
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chan->ramfc->instance >> 8);
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nv_wo32(dev, ramfc, 0x88/4, chan->cache->instance >> 10);
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nv_wo32(dev, ramfc, 0x98/4, chan->ramin->instance >> 12);
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}
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dev_priv->engine.instmem.flush(dev);
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nv50_fifo_channel_enable(dev, chan->id);
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nv50_fifo_playlist_update(dev);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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return 0;
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}
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void
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nv50_fifo_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct nouveau_gpuobj_ref *ramfc = chan->ramfc;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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/* This will ensure the channel is seen as disabled. */
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chan->ramfc = NULL;
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nv50_fifo_channel_disable(dev, chan->id);
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/* Dummy channel, also used on ch 127 */
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if (chan->id == 0)
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nv50_fifo_channel_disable(dev, 127);
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nv50_fifo_playlist_update(dev);
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nouveau_gpuobj_ref_del(dev, &ramfc);
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nouveau_gpuobj_ref_del(dev, &chan->cache);
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}
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int
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nv50_fifo_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
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struct nouveau_gpuobj *cache = chan->cache->gpuobj;
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int ptr, cnt;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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nv_wr32(dev, 0x3330, nv_ro32(dev, ramfc, 0x00/4));
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nv_wr32(dev, 0x3334, nv_ro32(dev, ramfc, 0x04/4));
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nv_wr32(dev, 0x3240, nv_ro32(dev, ramfc, 0x08/4));
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nv_wr32(dev, 0x3320, nv_ro32(dev, ramfc, 0x0c/4));
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nv_wr32(dev, 0x3244, nv_ro32(dev, ramfc, 0x10/4));
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nv_wr32(dev, 0x3328, nv_ro32(dev, ramfc, 0x14/4));
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nv_wr32(dev, 0x3368, nv_ro32(dev, ramfc, 0x18/4));
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nv_wr32(dev, 0x336c, nv_ro32(dev, ramfc, 0x1c/4));
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nv_wr32(dev, 0x3370, nv_ro32(dev, ramfc, 0x20/4));
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nv_wr32(dev, 0x3374, nv_ro32(dev, ramfc, 0x24/4));
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nv_wr32(dev, 0x3378, nv_ro32(dev, ramfc, 0x28/4));
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nv_wr32(dev, 0x337c, nv_ro32(dev, ramfc, 0x2c/4));
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nv_wr32(dev, 0x3228, nv_ro32(dev, ramfc, 0x30/4));
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nv_wr32(dev, 0x3364, nv_ro32(dev, ramfc, 0x34/4));
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nv_wr32(dev, 0x32a0, nv_ro32(dev, ramfc, 0x38/4));
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nv_wr32(dev, 0x3224, nv_ro32(dev, ramfc, 0x3c/4));
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nv_wr32(dev, 0x324c, nv_ro32(dev, ramfc, 0x40/4));
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nv_wr32(dev, 0x2044, nv_ro32(dev, ramfc, 0x44/4));
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nv_wr32(dev, 0x322c, nv_ro32(dev, ramfc, 0x48/4));
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nv_wr32(dev, 0x3234, nv_ro32(dev, ramfc, 0x4c/4));
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nv_wr32(dev, 0x3340, nv_ro32(dev, ramfc, 0x50/4));
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nv_wr32(dev, 0x3344, nv_ro32(dev, ramfc, 0x54/4));
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nv_wr32(dev, 0x3280, nv_ro32(dev, ramfc, 0x58/4));
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nv_wr32(dev, 0x3254, nv_ro32(dev, ramfc, 0x5c/4));
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nv_wr32(dev, 0x3260, nv_ro32(dev, ramfc, 0x60/4));
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nv_wr32(dev, 0x3264, nv_ro32(dev, ramfc, 0x64/4));
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nv_wr32(dev, 0x3268, nv_ro32(dev, ramfc, 0x68/4));
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nv_wr32(dev, 0x326c, nv_ro32(dev, ramfc, 0x6c/4));
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nv_wr32(dev, 0x32e4, nv_ro32(dev, ramfc, 0x70/4));
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nv_wr32(dev, 0x3248, nv_ro32(dev, ramfc, 0x74/4));
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nv_wr32(dev, 0x2088, nv_ro32(dev, ramfc, 0x78/4));
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nv_wr32(dev, 0x2058, nv_ro32(dev, ramfc, 0x7c/4));
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nv_wr32(dev, 0x2210, nv_ro32(dev, ramfc, 0x80/4));
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cnt = nv_ro32(dev, ramfc, 0x84/4);
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for (ptr = 0; ptr < cnt; ptr++) {
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nv_wr32(dev, NV40_PFIFO_CACHE1_METHOD(ptr),
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nv_ro32(dev, cache, (ptr * 2) + 0));
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nv_wr32(dev, NV40_PFIFO_CACHE1_DATA(ptr),
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nv_ro32(dev, cache, (ptr * 2) + 1));
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}
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, cnt << 2);
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nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
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/* guessing that all the 0x34xx regs aren't on NV50 */
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if (dev_priv->chipset != 0x50) {
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nv_wr32(dev, 0x340c, nv_ro32(dev, ramfc, 0x88/4));
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nv_wr32(dev, 0x3400, nv_ro32(dev, ramfc, 0x8c/4));
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nv_wr32(dev, 0x3404, nv_ro32(dev, ramfc, 0x90/4));
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nv_wr32(dev, 0x3408, nv_ro32(dev, ramfc, 0x94/4));
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nv_wr32(dev, 0x3410, nv_ro32(dev, ramfc, 0x98/4));
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}
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nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
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return 0;
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}
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int
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nv50_fifo_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_gpuobj *ramfc, *cache;
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struct nouveau_channel *chan = NULL;
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int chid, get, put, ptr;
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NV_DEBUG(dev, "\n");
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chid = pfifo->channel_id(dev);
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if (chid < 1 || chid >= dev_priv->engine.fifo.channels - 1)
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return 0;
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chan = dev_priv->fifos[chid];
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if (!chan) {
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NV_ERROR(dev, "Inactive channel on PFIFO: %d\n", chid);
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return -EINVAL;
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}
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ramfc = chan->ramfc->gpuobj;
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cache = chan->cache->gpuobj;
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nv_wo32(dev, ramfc, 0x00/4, nv_rd32(dev, 0x3330));
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nv_wo32(dev, ramfc, 0x04/4, nv_rd32(dev, 0x3334));
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nv_wo32(dev, ramfc, 0x08/4, nv_rd32(dev, 0x3240));
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nv_wo32(dev, ramfc, 0x0c/4, nv_rd32(dev, 0x3320));
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nv_wo32(dev, ramfc, 0x10/4, nv_rd32(dev, 0x3244));
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nv_wo32(dev, ramfc, 0x14/4, nv_rd32(dev, 0x3328));
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nv_wo32(dev, ramfc, 0x18/4, nv_rd32(dev, 0x3368));
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nv_wo32(dev, ramfc, 0x1c/4, nv_rd32(dev, 0x336c));
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nv_wo32(dev, ramfc, 0x20/4, nv_rd32(dev, 0x3370));
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nv_wo32(dev, ramfc, 0x24/4, nv_rd32(dev, 0x3374));
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nv_wo32(dev, ramfc, 0x28/4, nv_rd32(dev, 0x3378));
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nv_wo32(dev, ramfc, 0x2c/4, nv_rd32(dev, 0x337c));
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nv_wo32(dev, ramfc, 0x30/4, nv_rd32(dev, 0x3228));
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nv_wo32(dev, ramfc, 0x34/4, nv_rd32(dev, 0x3364));
|
|
nv_wo32(dev, ramfc, 0x38/4, nv_rd32(dev, 0x32a0));
|
|
nv_wo32(dev, ramfc, 0x3c/4, nv_rd32(dev, 0x3224));
|
|
nv_wo32(dev, ramfc, 0x40/4, nv_rd32(dev, 0x324c));
|
|
nv_wo32(dev, ramfc, 0x44/4, nv_rd32(dev, 0x2044));
|
|
nv_wo32(dev, ramfc, 0x48/4, nv_rd32(dev, 0x322c));
|
|
nv_wo32(dev, ramfc, 0x4c/4, nv_rd32(dev, 0x3234));
|
|
nv_wo32(dev, ramfc, 0x50/4, nv_rd32(dev, 0x3340));
|
|
nv_wo32(dev, ramfc, 0x54/4, nv_rd32(dev, 0x3344));
|
|
nv_wo32(dev, ramfc, 0x58/4, nv_rd32(dev, 0x3280));
|
|
nv_wo32(dev, ramfc, 0x5c/4, nv_rd32(dev, 0x3254));
|
|
nv_wo32(dev, ramfc, 0x60/4, nv_rd32(dev, 0x3260));
|
|
nv_wo32(dev, ramfc, 0x64/4, nv_rd32(dev, 0x3264));
|
|
nv_wo32(dev, ramfc, 0x68/4, nv_rd32(dev, 0x3268));
|
|
nv_wo32(dev, ramfc, 0x6c/4, nv_rd32(dev, 0x326c));
|
|
nv_wo32(dev, ramfc, 0x70/4, nv_rd32(dev, 0x32e4));
|
|
nv_wo32(dev, ramfc, 0x74/4, nv_rd32(dev, 0x3248));
|
|
nv_wo32(dev, ramfc, 0x78/4, nv_rd32(dev, 0x2088));
|
|
nv_wo32(dev, ramfc, 0x7c/4, nv_rd32(dev, 0x2058));
|
|
nv_wo32(dev, ramfc, 0x80/4, nv_rd32(dev, 0x2210));
|
|
|
|
put = (nv_rd32(dev, NV03_PFIFO_CACHE1_PUT) & 0x7ff) >> 2;
|
|
get = (nv_rd32(dev, NV03_PFIFO_CACHE1_GET) & 0x7ff) >> 2;
|
|
ptr = 0;
|
|
while (put != get) {
|
|
nv_wo32(dev, cache, ptr++,
|
|
nv_rd32(dev, NV40_PFIFO_CACHE1_METHOD(get)));
|
|
nv_wo32(dev, cache, ptr++,
|
|
nv_rd32(dev, NV40_PFIFO_CACHE1_DATA(get)));
|
|
get = (get + 1) & 0x1ff;
|
|
}
|
|
|
|
/* guessing that all the 0x34xx regs aren't on NV50 */
|
|
if (dev_priv->chipset != 0x50) {
|
|
nv_wo32(dev, ramfc, 0x84/4, ptr >> 1);
|
|
nv_wo32(dev, ramfc, 0x88/4, nv_rd32(dev, 0x340c));
|
|
nv_wo32(dev, ramfc, 0x8c/4, nv_rd32(dev, 0x3400));
|
|
nv_wo32(dev, ramfc, 0x90/4, nv_rd32(dev, 0x3404));
|
|
nv_wo32(dev, ramfc, 0x94/4, nv_rd32(dev, 0x3408));
|
|
nv_wo32(dev, ramfc, 0x98/4, nv_rd32(dev, 0x3410));
|
|
}
|
|
|
|
dev_priv->engine.instmem.flush(dev);
|
|
|
|
/*XXX: probably reload ch127 (NULL) state back too */
|
|
nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, 127);
|
|
return 0;
|
|
}
|
|
|