69f1d1a6ac
* 'next/devel' of ssh://master.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (128 commits) ARM: S5P64X0: External Interrupt Support ARM: EXYNOS4: Enable MFC on Samsung NURI ARM: EXYNOS4: Enable MFC on universal_c210 ARM: S5PV210: Enable MFC on Goni ARM: S5P: Add support for MFC device ARM: EXYNOS4: Add support FIMD on SMDKC210 ARM: EXYNOS4: Add platform device and helper functions for FIMD ARM: EXYNOS4: Add resource definition for FIMD ARM: EXYNOS4: Change devname for FIMD clkdev ARM: SAMSUNG: Add IRQ_I2S0 definition ARM: SAMSUNG: Add platform device for idma ARM: EXYNOS4: Add more registers to be saved and restored for PM ARM: EXYNOS4: Add more register addresses of CMU ARM: EXYNOS4: Add platform device for dwmci driver ARM: EXYNOS4: configure rtc-s3c on NURI ARM: EXYNOS4: configure MAX8903 secondary charger on NURI ARM: EXYNOS4: configure ADC on NURI ARM: EXYNOS4: configure MAX17042 fuel gauge on NURI ARM: EXYNOS4: configure regulators and PMIC(MAX8997) on NURI ARM: EXYNOS4: Increase NR_IRQS for devices with more IRQs ... Fix up tons of silly conflicts: - arch/arm/mach-davinci/include/mach/psc.h - arch/arm/mach-exynos4/Kconfig - arch/arm/mach-exynos4/mach-smdkc210.c - arch/arm/mach-exynos4/pm.c - arch/arm/mach-imx/mm-imx1.c - arch/arm/mach-imx/mm-imx21.c - arch/arm/mach-imx/mm-imx25.c - arch/arm/mach-imx/mm-imx27.c - arch/arm/mach-imx/mm-imx31.c - arch/arm/mach-imx/mm-imx35.c - arch/arm/mach-mx5/mm.c - arch/arm/mach-s5pv210/mach-goni.c - arch/arm/mm/Kconfig
96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/*
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* Copyright (C) 1999,2000 Arm Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* - add MX31 specific definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <mach/common.h>
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#include <mach/devices-common.h>
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#include <mach/hardware.h>
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#include <mach/mx25.h>
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#include <mach/iomux-v3.h>
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#include <mach/irqs.h>
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/*
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* This table defines static virtual address mappings for I/O regions.
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* These are the mappings common across all MX25 boards.
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*/
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static struct map_desc mx25_io_desc[] __initdata = {
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imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
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imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
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imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
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};
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/*
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* This function initializes the memory map. It is called during the
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* system startup to create static physical to virtual memory mappings
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* for the IO modules.
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*/
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void __init mx25_map_io(void)
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{
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iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
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}
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void __init imx25_init_early(void)
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{
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mxc_set_cpu_type(MXC_CPU_MX25);
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mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
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}
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void __init mx25_init_irq(void)
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{
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mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
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}
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static struct sdma_script_start_addrs imx25_sdma_script __initdata = {
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.ap_2_ap_addr = 729,
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.uart_2_mcu_addr = 904,
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.per_2_app_addr = 1255,
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.mcu_2_app_addr = 834,
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.uartsh_2_mcu_addr = 1120,
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.per_2_shp_addr = 1329,
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.mcu_2_shp_addr = 1048,
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.ata_2_mcu_addr = 1560,
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.mcu_2_ata_addr = 1479,
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.app_2_per_addr = 1189,
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.app_2_mcu_addr = 770,
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.shp_2_per_addr = 1407,
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.shp_2_mcu_addr = 979,
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};
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static struct sdma_platform_data imx25_sdma_pdata __initdata = {
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.sdma_version = 2,
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.fw_name = "sdma-imx25.bin",
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.script_addrs = &imx25_sdma_script,
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};
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void __init imx25_soc_init(void)
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{
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/* i.mx25 has the i.mx31 type gpio */
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mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
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mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
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mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
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mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
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imx_add_imx_sdma(MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
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}
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